Sampling, ADC & DAC
The NyquistβShannon theorem, aliasing, quantization noise, ADC architectures, and DAC circuits β the complete analog-to-digital-to-analog chain.
1. NyquistβShannon Sampling Theorem
A continuous-time signal \(x(t)\) with maximum frequency component \(f_{max}\)can be perfectly reconstructed from its samples if and only if the sampling rate satisfies:
\[ f_s \;\geq\; 2\,f_{max} \]
The Nyquist rate is \(f_{Nyq} = 2\,f_{max}\). Sampling below this rate causes aliasing.
Sampling is mathematically equivalent to multiplying \(x(t)\) by an impulse train\(p(t) = \sum_n \delta(t - nT_s)\) where \(T_s = 1/f_s\). In the frequency domain, this replicates the spectrum at multiples of \(f_s\). If \(f_s < 2f_{max}\), the replicas overlap β aliasing β and the original signal cannot be recovered by any low-pass filter.
In practice, an anti-aliasing filter (low-pass, cutoff \(f_s/2\)) is applied before sampling to remove frequencies that would alias. Audio CD uses \(f_s = 44.1\) kHz to cover the 20 Hzβ20 kHz audible range with margin.
2. The Sampling Process
A continuous-time signal is sampled at rate \(f_s\), yielding discrete samples \(x[n] = x(nT_s)\). A low-pass reconstruction filter recovers the original waveform perfectly when \(f_s \geq 2f_{max}\).
3. Quantization
An N-bit ADC maps a continuous amplitude to one of \(2^N\) discrete levels. The step size (least significant bit, LSB) is:
\[ \Delta V \;=\; \frac{V_{ref}}{2^N} \]
Quantization introduces an error uniformly distributed in \([-\Delta V/2,\, \Delta V/2]\). The resulting quantization noise power is \(\sigma_q^2 = \Delta V^2/12\), giving the well-known SNR formula for a full-scale sinusoidal input:
\[ \text{SNR} \;=\; 6.02\,N \;+\; 1.76 \;\text{dB} \]
Each additional bit adds ~6 dB of dynamic range
A 16-bit audio converter achieves ~98 dB SNR. A 24-bit professional converter reaches ~146 dB, well beyond the noise floor of any analog circuit.
4. ADC Architectures
Flash ADC
Uses 2^N β 1 comparators in parallel. Fastest architecture β single-clock conversion. Power and area scale exponentially with bits.
SAR ADC
Successive approximation register performs binary search. N clock cycles per conversion. Excellent power efficiency β dominant in microcontrollers.
Sigma-Delta (Ξ£Ξ)
Oversamples and noise-shapes quantization error to high frequencies, then decimates. Highest resolution; used in audio and precision measurement.
All ADCs require a sample-and-hold (S/H) circuit that freezes the input voltage during conversion. Aperture jitter β uncertainty in sampling instant β limits high-frequency performance: \(\text{SNR}_{jitter} = -20\log_{10}(2\pi f_{in} t_j)\).
5. DAC Architectures
A Digital-to-Analog Converter maps an N-bit binary code to an analog voltage. The ideal output is \(V_{out} = D \cdot \Delta V\) where \(D\)is the decimal value of the code.
R-2R Ladder DAC
Uses only two resistor values (R and 2R) in a ladder network. Only 2N resistors needed for N bits β compared to \(2^N\) for weighted-resistor DACs. Output: \(V_{out} = V_{ref}(b_{N-1}/2 + b_{N-2}/4 + \cdots)\)
Widely used β excellent matching, monotonic, simple layout.
Weighted-Resistor DAC
Each bit switches a resistor of value \(R/2^k\) (MSB = R, LSB = \(R/2^{N-1}\)). Simple analysis but resistors span a \(2^{N-1}\) range β impractical for N > 8 due to matching requirements.
Mainly pedagogical; R-2R preferred in practice.
Key DAC specifications: DNL (differential nonlinearity β deviation of each step from ideal \(\Delta V\)), INL(integral nonlinearity β cumulative error), and settling time(time to reach final value within \(1/2\) LSB).
Python Simulation
Demonstrates proper sampling vs. aliasing, quantization at different bit depths, SNR vs. N, R-2R DAC output, and quantization noise spectra.
Click Run to execute the Python code
Code will be executed with Python 3 on the server