Electronics/Part VII: Modern Electronics/RF, VLSI & Photonics

Chapter 21: RF, VLSI & Photonics

Three advanced technology domains converge in modern systems: RF electronics enables wireless communication from Bluetooth to 5G; VLSI design packs billions of FinFET transistors onto a chip the size of a fingernail; and photonics transmits information at the speed of light through optical fibres spanning continents. This chapter surveys the key principles of each domain.

Part A — RF Electronics

21.1 Smith Chart & S-Parameters

The Smith chart is a graphical tool for visualising complex impedance on a normalised polar plot. Any complex impedance \(Z = R + jX\) is mapped to the reflection coefficient:

\( \Gamma = \frac{Z - Z_0}{Z + Z_0}, \quad |\Gamma| \leq 1 \)

where \(Z_0 = 50\,\Omega\) is the reference impedance. The chart is used to design impedance-matching networks (L, π, T topologies) by tracing paths along constant-resistance and constant-reactance circles.

S-parameters (scattering parameters) describe multi-port networks at RF frequencies where voltage and current are not well-defined independently. For a two-port network:

\( \begin{pmatrix} b_1 \\ b_2 \end{pmatrix} = \begin{pmatrix} S_{11} & S_{12} \\ S_{21} & S_{22} \end{pmatrix} \begin{pmatrix} a_1 \\ a_2 \end{pmatrix} \)

S₁₁

Input reflection coefficient — return loss

S₂₁

Forward transmission gain — insertion loss

S₁₂

Reverse isolation

S₂₂

Output reflection coefficient

21.2 Low-Noise Amplifier & Noise Figure

The Low-Noise Amplifier (LNA) is the first active stage after the antenna in any receiver. Its job is to amplify the weak received signal while adding as little thermal noise as possible. Noise Figure (NF) quantifies this degradation:

\( NF = 10 \log_{10}(F), \quad F = \frac{SNR_{\text{in}}}{SNR_{\text{out}}} \geq 1 \)

For a cascade of stages (Friis formula), the total noise figure is dominated by the first stage:

\( F_{\text{total}} = F_1 + \frac{F_2 - 1}{G_1} + \frac{F_3 - 1}{G_1 G_2} + \cdots \)

A typical LNA has NF < 1 dB and gain of 15–20 dB. The minimum NF is set by the transistor technology and bias point. CMOS LNAs in 28 nm achieve NF ≈ 0.5 dB at 2.4 GHz. At mmWave frequencies (24–86 GHz for 5G), SiGe HBT or III-V (GaAs, InP) transistors are used for their superior high-frequency fT (transit frequency).

21.3 Link Budget

A link budget tallies all gains and losses in a wireless system to determine the received signal power and verify it exceeds the receiver sensitivity. The Friis transmission equation:

\( P_r = P_t + G_t + G_r - L_{\text{path}} - L_{\text{misc}} \quad \text{(dBm)} \)

where free-space path loss \(L_{\text{path}} = 20\log_{10}(4\pi d f / c)\) in dB,\(G_t, G_r\) are antenna gains, and \(L_{\text{misc}}\) includes cable, connector, and atmospheric losses. The link margin \(= P_r - P_{\text{sens}}\) must be positive (typically 10–20 dB) to ensure a reliable link under fading.

Part B — VLSI Design

21.4 Moore's Law & CMOS Fabrication

Gordon Moore (1965) observed that the number of transistors on a chip doubled roughly every year (revised to every two years in 1975). This empirical prediction drove the semiconductor industry for 50 years, enabling exponential improvements in computing power at constant cost.

CMOS (Complementary Metal-Oxide-Semiconductor) fabrication uses paired NMOS and PMOS transistors. Static CMOS gates draw near-zero DC current (only the short-circuit current during switching), making them the dominant technology for low-power digital logic.

The CMOS dynamic power dissipation:

\( P_{\text{dynamic}} = \alpha \cdot C_L \cdot V_{DD}^2 \cdot f \)

where \(\alpha\) is activity factor (0–1), \(C_L\) is load capacitance, \(V_{DD}\) is supply voltage, and \(f\) is clock frequency. Voltage scaling \(V_{DD}\) is the most effective power reduction lever since power scales as \(V^2\). Below ~22 nm, leakage current becomes comparable to dynamic power, driving the need for FinFET and GAA (gate-all-around) transistors.

21.5 Standard Cell Design & Synthesis Flow

Modern VLSI design uses a standard cell methodology: the foundry provides a library of pre-characterised logic cells (NAND2, INV, DFF, MUX2, …) at fixed height with variable width. The EDA flow converts RTL (Register Transfer Level) hardware description to a manufacturable GDSII layout:

1. RTL Design

Write synthesisable Verilog/VHDL. Specify functionality, not gates. Simulate with testbenches.

2. Logic Synthesis

Tools (Synopsys Design Compiler, Cadence Genus) map RTL to standard cells. Optimise for area, timing, or power given constraints.

3. Floor Planning

Place macro blocks (memories, IP cores), define power rings, create I/O ring. Pin assignment.

4. Place & Route

Automatically place standard cells in rows. Route metal interconnect across multiple layers (M1–M12+). Clock tree synthesis (CTS) for zero-skew distribution.

5. Timing Analysis (STA)

Static Timing Analysis checks setup and hold violations across all PVT corners. Setup: data must arrive t_setup before clock edge. Hold: data must be stable for t_hold after clock edge.

6. Sign-off & Tapeout

DRC (design rule check), LVS (layout vs schematic), IR drop, electromigration checks. Export GDSII to foundry.

21.6 FinFET Technology

A FinFET (fin field-effect transistor) is a 3D transistor where the channel is a thin vertical silicon fin surrounded by the gate on three sides. This improves gate control over the channel, drastically reducing short-channel effects and subthreshold leakage that plagued planar MOSFETs below 28 nm.

Planar MOSFET (>28 nm)

Gate sits on top of the flat silicon channel. Gate length shrinking below 25 nm causes drain-induced barrier lowering (DIBL) — the drain voltage pulls down the source barrier, causing leakage even when gate is off.

FinFET (≤22 nm)

Gate wraps around three sides of the fin. Effective gate control is greatly increased. Multiple fins can be connected in parallel to scale drive current. Introduced at 22 nm by Intel (2011) as Tri-gate, now universal below 16 nm.

Beyond 3 nm, Gate-All-Around (GAA) nanosheet transistors (Samsung 3 nm, TSMC N2) surround the channel on all four sides for even better electrostatic control. The effective mobility in a 3 nm nanosheet device: \(\mu_{\text{eff}} \approx 200 \text{ cm}^2/\text{V·s}\) (electrons), \(70 \text{ cm}^2/\text{V·s}\) (holes).

Part C — Photonics

Fiber Optic: Total Internal Reflection

21.7 Fiber Optics & Total Internal Reflection

Light is confined in an optical fiber by total internal reflection (TIR) at the core-cladding interface. TIR occurs when the angle of incidence exceeds the critical angle:

\( \theta_c = \arcsin\!\left(\frac{n_2}{n_1}\right), \quad n_1 > n_2 \)

The Numerical Aperture (NA) defines the acceptance cone of the fiber:

\( NA = \sqrt{n_1^2 - n_2^2} = n_0 \sin\theta_{\max} \)

Standard single-mode fiber (SMF-28): core 8–9 µm, cladding 125 µm, NA = 0.14. Guides a single spatial mode at 1310 nm and 1550 nm (the telecom C-band). Multi-mode fiber (50/125 µm) supports many modes but suffers modal dispersion limiting bandwidth×distance to ~500 MHz·km vs >10 THz·km for SMF.

Attenuation at 1550 nm: ≈ 0.2 dB/km (Rayleigh scattering + infrared absorption). With optical amplifiers (EDFA — Erbium-Doped Fiber Amplifier) every 80 km, transoceanic links span 10 000 km carrying 100+ Tbit/s using wavelength-division multiplexing (WDM) with 96 channels at 100 GHz spacing.

21.8 LEDs, Laser Diodes & Photodetectors

LED

Forward-biased PN junction emits photons by spontaneous emission. Photon energy hf = E_g (bandgap). GaAs: 870 nm (IR); GaN: 450 nm (blue); InGaN: 530 nm (green). Wall-plug efficiency up to 80% (modern LEDs). Used in displays, indicators, optical isolation, and solid-state lighting.

Laser Diode

Stimulated emission in a Fabry-Pérot or DFB (distributed feedback) cavity. Coherent, narrow linewidth (<1 MHz), low divergence. Used in fiber-optic transmitters, LiDAR, optical disk drives. DFB lasers at 1550 nm for telecom: side-mode suppression ratio >40 dB, directly modulated up to 10 Gbit/s.

Photodetector

Reverse-biased PN or PIN diode converts photons to photocurrent. Responsivity R = I_ph/P_opt (A/W). Si: 0.6 A/W at 850 nm; InGaAs PIN: 0.8–0.9 A/W at 1550 nm. Avalanche photodiode (APD): internal gain via impact ionisation; used in long-haul receivers and LiDAR.

21.9 Optical Communication Systems

A coherent optical transceiver (used in 100G/400G Ethernet and 800G data-centre interconnects) uses DP-QPSK or 16-QAM modulation on both polarisation states of the fiber, achieving spectral efficiencies of 4–8 bit/s/Hz. The received optical power must exceed the sensitivity:

\( P_{\text{sens}} = \frac{N_0 \cdot B \cdot \text{SNR}_{\min}}{R_{\text{det}}} \)

where \(N_0\) is noise spectral density, \(B\) is electrical bandwidth, \(\text{SNR}_{\min}\) is the required SNR for the chosen modulation format (e.g. 15 dB for 16-QAM at BER = 10⁻³), and \(R_{\text{det}}\) is detector responsivity.

Silicon Photonics: integrating optical waveguides, modulators (Mach-Zehnder), and photodetectors on standard CMOS wafers enables co-packaged optics — optical I/O directly on a CPU/GPU package. Intel, TSMC, and GlobalFoundries all offer silicon photonics platforms at 90–130 nm node.

Python: Moore's Law Visualisation

The left panel plots transistor count vs year on a log scale for key processor milestones from the Intel 4004 (1971) to Apple M3 (2023), with the theoretical Moore's Law doubling trendline. The right panel plots CMOS process node shrinkage vs the ideal Dennard scaling prediction, annotating the ~2005 breakdown of Dennard scaling that shifted the industry to multi-core designs.

Python

script.py119 lines

import numpy as np
import matplotlib
matplotlib.use('Agg')
import matplotlib.pyplot as plt

fig, axes = plt.subplots(1, 2, figsize=(16, 7))
fig.patch.set_facecolor('#0a0a1a')

# Historical transistor count data (year, count, label)
milestones = [
    (1971, 2300,       'Intel 4004'),
    (1974, 4500,       'Intel 8080'),
    (1978, 29000,      'Intel 8086'),
    (1982, 134000,     'Intel 286'),
    (1985, 275000,     'Intel 386'),
    (1989, 1.2e6,      'Intel 486'),
    (1993, 3.1e6,      'Pentium'),
    (1997, 7.5e6,      'Pentium II'),
    (1999, 9.5e6,      'Pentium III'),
    (2000, 42e6,       'Pentium 4'),
    (2003, 77e6,       'Pentium M'),
    (2006, 291e6,      'Core 2 Duo'),
    (2008, 731e6,      'Core i7 (45nm)'),
    (2010, 1.17e9,     'Core i7 (32nm)'),
    (2012, 1.4e9,      'Ivy Bridge'),
    (2014, 1.9e9,      'Broadwell'),
    (2017, 3.3e9,      'Kaby Lake'),
    (2019, 8.0e9,      'Ice Lake'),
    (2020, 16e9,       'Tiger Lake'),
    (2021, 57e9,       'Apple M1 Pro'),
    (2022, 114e9,      'Apple M2'),
    (2023, 134e9,      'Apple M3'),
]

years = np.array([m[0] for m in milestones])
counts = np.array([m[1] for m in milestones])
labels = [m[2] for m in milestones]

# --- Panel 1: Transistor count vs year (log scale) ---
ax1 = axes[0]
ax1.semilogy(years, counts, 'o-', color='#34d399', linewidth=1.8, markersize=6, markerfacecolor='#22d3ee', markeredgecolor='#34d399', zorder=3)

# Annotate key milestones
annotate_indices = [0, 4, 8, 12, 16, 19, 21]
for idx in annotate_indices:
    ax1.annotate(labels[idx], (years[idx], counts[idx]),
                 textcoords='offset points', xytext=(6, 4),
                 fontsize=7.5, color='#fbbf24', zorder=5)

# Moore's law trend line: doubles every 2 years from 1971
year_fit = np.linspace(1970, 2026, 300)
moore_line = 2300 * 2 ** ((year_fit - 1971) / 2)
ax1.semilogy(year_fit, moore_line, '--', color='#f87171', linewidth=1.5, alpha=0.7, label="Moore's Law (2x/2yr)")

ax1.set_xlabel('Year', fontsize=12, color='white')
ax1.set_ylabel('Transistor Count', fontsize=12, color='white')
ax1.set_title("Moore's Law: Transistor Count 1971-2023", fontsize=13, color='white', fontweight='bold')
ax1.legend(fontsize=10, facecolor='#1a1a2e', edgecolor='#34d399', labelcolor='white')
ax1.set_facecolor('#0a0a1a')
ax1.tick_params(colors='white')
ax1.grid(True, alpha=0.2, color='#34d399', which='both')
for spine in ax1.spines.values():
    spine.set_color('#34d399')

# Add node annotations on secondary axis
ax1_top = ax1.twiny()
node_map = {1989: '1000nm', 2000: '180nm', 2007: '65nm', 2012: '22nm', 2017: '10nm', 2020: '5nm', 2022: '3nm'}
ax1_top.set_xlim(ax1.get_xlim())
ax1_top.set_xticks(list(node_map.keys()))
ax1_top.set_xticklabels(list(node_map.values()), fontsize=7, rotation=45, color='#a78bfa')
ax1_top.tick_params(colors='#a78bfa')

# --- Panel 2: Process node vs year & transistor density ---
ax2 = axes[1]

# Process node (nm) over time
node_data = [
    (1971, 10000), (1974, 6000), (1978, 3000), (1982, 1500),
    (1985, 1000), (1989, 800), (1993, 600), (1997, 350),
    (1999, 250), (2000, 180), (2003, 130), (2006, 65),
    (2008, 45), (2010, 32), (2012, 22), (2014, 14),
    (2017, 10), (2019, 7), (2020, 5), (2022, 3), (2023, 2),
]
nd_years = [d[0] for d in node_data]
nd_nodes = [d[1] for d in node_data]

ax2.semilogy(nd_years, nd_nodes, 's-', color='#22d3ee', linewidth=2, markersize=6,
             markerfacecolor='#0e7490', markeredgecolor='#22d3ee', label='Process Node (nm)')

# Ideal Dennard scaling: node shrinks sqrt(2) every 2 years
year_d = np.linspace(1970, 2024, 300)
dennard = 10000 * (1 / np.sqrt(2)) ** ((year_d - 1971) / 2)
ax2.semilogy(year_d, dennard, '--', color='#fbbf24', linewidth=1.5, alpha=0.7, label='Dennard Scaling ideal')

ax2.axvline(2005, color='#f87171', linestyle=':', linewidth=1.5, alpha=0.8)
ax2.text(2006, 3000, 'Dennard
Scaling
End ~2005', fontsize=8, color='#f87171')

ax2.set_xlabel('Year', fontsize=12, color='white')
ax2.set_ylabel('Process Node (nm)', fontsize=12, color='white')
ax2.set_title('CMOS Process Node Shrinkage', fontsize=13, color='white', fontweight='bold')
ax2.legend(fontsize=10, facecolor='#1a1a2e', edgecolor='#34d399', labelcolor='white')
ax2.set_facecolor('#0a0a1a')
ax2.tick_params(colors='white')
ax2.grid(True, alpha=0.2, color='#34d399', which='both')
for spine in ax2.spines.values():
    spine.set_color('#34d399')

plt.tight_layout()
plt.savefig('output.png', dpi=150, bbox_inches='tight', facecolor='#0a0a1a')
plt.show()
print("Moore's Law: transistor count doubles approximately every 2 years (1965-Gordon Moore)")
print("Intel 4004 (1971): 2300 transistors, 10 micron process")
print("Apple M2 (2022): ~114 billion transistors, 3 nm TSMC process")
print("Dennard Scaling (1974): as node shrinks, power density stays constant")
print("Dennard Scaling ended ~2005: power density now increases => multi-core shift")
print("FinFET (3D transistor) introduced at 22nm (Intel 2011) to control leakage")

Click Run to execute the Python code

Code will be executed with Python 3 on the server

Key Equations

Reflection coefficient (RF):\( \Gamma = (Z - Z_0)/(Z + Z_0) \) — maps impedance to Smith chart

Friis noise figure cascade:\( F_{\text{tot}} = F_1 + (F_2-1)/G_1 + (F_3-1)/(G_1 G_2) + \cdots \)

CMOS dynamic power:\( P = \alpha C_L V_{DD}^2 f \)

Critical angle (fiber):\( \theta_c = \arcsin(n_2/n_1) \)

Numerical aperture:\( NA = \sqrt{n_1^2 - n_2^2} \)

Free-space path loss:\( L_{\text{path}} = 20\log_{10}(4\pi d f / c) \text{ dB} \)

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