Part II: Semiconductor Physics | Chapter 6

Transistors: BJT & MOSFET

The active devices at the heart of every amplifier, logic gate, and integrated circuit.

Bipolar Junction Transistor (BJT)

A BJT consists of two back-to-back PN junctions — either NPN or PNP. In an NPN transistor a thin p-type base separates the n-type emitter and collector. The base current controls a much larger collector current.

Active Region

E-B forward biased, C-B reverse biased. \( I_C = \beta I_B \). Amplification is possible here.

Saturation

Both junctions forward biased. \( V_{CE} \approx 0.2 \) V. Transistor acts as closed switch.

Cutoff

Both junctions reverse biased. \( I_C \approx 0 \). Transistor acts as open switch.

The current gain \( \beta \) (also written \( h_{FE} \)) relates collector to base current:

\[ I_C = \beta I_B, \qquad I_E = I_B + I_C = (\beta + 1)I_B \]

The Ebers-Moll model captures all regions with two coupled diode equations. In the active region it reduces to:

\[ I_C = I_S \exp\!\left(\frac{V_{BE}}{V_T}\right)\!\left(1 + \frac{V_{CE}}{V_A}\right) \]

The factor \( (1 + V_{CE}/V_A) \) represents the Early effect: the slight increase in \( I_C \)with \( V_{CE} \) due to base-width modulation, characterised by Early voltage \( V_A \approx 50\text{–}200 \) V.

MOSFET: Metal-Oxide-Semiconductor FET

The MOSFET is a voltage-controlled device. In an NMOS transistor, a positive gate voltage creates an inversion layer (channel) between the n-type source and drain, allowing current to flow.

MOSFET Operating Regions

Cutoff (\( V_{GS} < V_{th} \))

No channel. \( I_D = 0 \). Gate voltage insufficient to invert the substrate.

Triode (\( V_{DS} < V_{GS} - V_{th} \))

Channel present end-to-end. Acts as a voltage-controlled resistor:

\[ I_D = K\!\left(V_{ov} - \frac{V_{DS}}{2}\right)\!V_{DS} \]

Saturation (\( V_{DS} \geq V_{GS} - V_{th} \))

Channel is pinched off. Current is controlled by \( V_{GS} \) alone:

\[ I_D = \frac{K}{2}(V_{GS} - V_{th})^2 \]

where \( V_{ov} = V_{GS} - V_{th} \) is the overdrive voltage and \( K = \mu_n C_{ox} W/L \)is the process transconductance parameter (\( \mu_n \): electron mobility, \( C_{ox} \): gate capacitance per unit area).

CMOS Inverter

Complementary MOS (CMOS) logic pairs an NMOS and PMOS transistor. In a CMOS inverter:

When \( V_{in} = V_{DD} \): NMOS ON, PMOS OFF → \( V_{out} = 0 \)
When \( V_{in} = 0 \): NMOS OFF, PMOS ON → \( V_{out} = V_{DD} \)

At no time are both transistors fully ON simultaneously, so static power consumption is nearly zero — the key advantage of CMOS over older NMOS-only logic families.

Small-Signal Models

For AC analysis around a DC bias point, both BJT and MOSFET are linearised. The MOSFET small-signal model introduces the transconductance \( g_m \) and output resistance \( r_o \):

\[ g_m = \frac{\partial I_D}{\partial V_{GS}}\bigg|_Q = \sqrt{2K I_D}, \qquad r_o = \frac{1}{\lambda I_D} \]

Python: BJT, MOSFET & CMOS Inverter

Plot BJT collector characteristics (with Early effect) for several base currents, NMOS output characteristics showing the triode/saturation boundary, and the CMOS inverter voltage transfer curve with switching point \( V_M \).

BJT Collector Curves, NMOS Output Characteristics & CMOS Inverter

Python

transistors_bjt_mosfet.py161 lines

import numpy as np
import matplotlib
matplotlib.use('Agg')
import matplotlib.pyplot as plt

# ---- BJT: Collector characteristics I_C vs V_CE ----
# Simple Ebers-Moll active region: I_C = beta * I_B
beta = 100.0        # current gain
V_CE_sat = 0.2      # saturation voltage
V_CE = np.linspace(0, 10, 500)

I_B_vals = np.array([10, 20, 30, 40, 50, 60]) * 1e-6   # uA
colors_bjt = ['#d1fae5', '#a7f3d0', '#6ee7b7', '#34d399', '#10b981', '#059669']

print('=== BJT Characteristics (NPN, beta=100) ===')
for I_B in I_B_vals:
    I_C_sat = beta * I_B
    print(f'I_B = {I_B*1e6:.0f} uA: I_C(active) = {I_C_sat*1000:.2f} mA, V_CE_sat = {V_CE_sat:.1f} V')

def bjt_ic(V_ce, I_b, beta_val=100, V_A=100):
    'Piecewise BJT: saturation for V_CE < V_CE_sat, active region with Early effect.'
    I_C_active = beta_val * I_b * (1 + V_ce / V_A)
    I_C = np.where(V_ce < V_CE_sat,
                   I_C_active * V_ce / V_CE_sat,
                   I_C_active)
    return I_C

# ---- MOSFET: NMOS output characteristics ----
# I_D = (K/2)*(V_GS - V_th)^2 in saturation (V_DS > V_GS - V_th)
# I_D = K*(V_GS - V_th - V_DS/2)*V_DS in triode (V_DS < V_GS - V_th)
K = 2e-3      # A/V^2  (process transconductance parameter)
V_th = 1.0    # threshold voltage, V
lambda_val = 0.02  # channel-length modulation, V^-1

V_DS = np.linspace(0, 10, 500)
V_GS_vals = np.array([1.5, 2.0, 2.5, 3.0, 3.5, 4.0])
colors_mos = ['#d1fae5', '#a7f3d0', '#6ee7b7', '#34d399', '#10b981', '#059669']

print()
print('=== NMOS Output Characteristics (K=2mA/V^2, Vth=1V) ===')
for V_GS in V_GS_vals:
    Vov = V_GS - V_th
    if Vov <= 0:
        print(f'V_GS={V_GS:.1f}V: OFF (V_GS < V_th)')
        continue
    I_D_sat = (K/2) * Vov**2 * (1 + lambda_val * 0)  # at onset of sat
    print(f'V_GS={V_GS:.1f}V: Vov={Vov:.1f}V, I_D(sat) = {I_D_sat*1000:.2f} mA')

def nmos_id(V_ds, V_gs, K_val=2e-3, Vth=1.0, lam=0.02):
    'NMOS drain current with channel-length modulation.'
    Vov = V_gs - Vth
    if Vov <= 0:
        return np.zeros_like(V_ds)
    V_dsat = Vov
    I_triode = K_val * (Vov - V_ds/2) * V_ds
    I_sat    = (K_val/2) * Vov**2 * (1 + lam * V_ds)
    return np.where(V_ds < V_dsat, I_triode, I_sat)

# ---- CMOS Inverter transfer curve ----
# NMOS: K_n=2mA/V^2, Vth_n=1V; PMOS: K_p=1mA/V^2, |Vth_p|=1V
VDD = 5.0
V_in = np.linspace(0, VDD, 2000)
K_n = 2e-3; K_p = 1e-3
Vth_n = 1.0; Vth_p = 1.0   # |Vth_p|

V_out = np.zeros_like(V_in)
for i, Vin in enumerate(V_in):
    # Solve by finding V_out where I_N = I_P (Newton iteration)
    Vov_n = Vin - Vth_n
    Vov_p = (VDD - Vin) - Vth_p  # PMOS with VDD reference
    if Vov_n <= 0:
        V_out[i] = VDD
    elif Vov_p <= 0:
        V_out[i] = 0.0
    else:
        # Simplified: binary switch approximation plus linear interpolation in transition
        V_out[i] = VDD * (1 - Vin / VDD)**2  # crude but illustrative

# Better: solve numerically
for i, Vin in enumerate(V_in):
    # Use bisection to find Vout s.t. I_N(Vin, Vout) = I_P(Vin, Vout)
    lo, hi = 0.0, VDD
    for _ in range(40):
        mid = (lo + hi) / 2
        # NMOS: V_GS_n=Vin, V_DS_n=mid
        ID_n = nmos_id(mid, Vin, K_n, Vth_n, 0.0)
        # PMOS: V_SG_p=VDD-Vin, V_SD_p=VDD-mid
        V_sg_p = VDD - Vin
        V_sd_p = VDD - mid
        Vov_p2 = V_sg_p - Vth_p
        if Vov_p2 <= 0:
            ID_p = 0.0
        else:
            ID_p = nmos_id(V_sd_p, V_sg_p, K_p, Vth_p, 0.0)
        if ID_n > ID_p:
            hi = mid
        else:
            lo = mid
    V_out[i] = (lo + hi) / 2

VM = V_in[np.argmin(np.abs(V_out - (VDD/2)))]
print()
print(f'CMOS Inverter switching point VM ~ {VM:.3f} V (VDD={VDD:.1f}V)')

# ---- Plots ----
fig, axes = plt.subplots(1, 3, figsize=(16, 5))
fig.patch.set_facecolor('#0a0a0a')
fig.suptitle('BJT & MOSFET Transistor Characteristics', color='#d1d5db', fontsize=13, y=0.98)
for ax in axes:
    ax.set_facecolor('#111827')
    for spine in ax.spines.values():
        spine.set_color('#374151')

# Plot 1: BJT collector characteristics
ax = axes[0]
for I_B, c in zip(I_B_vals, colors_bjt):
    IC = bjt_ic(V_CE, I_B) * 1000   # mA
    ax.plot(V_CE, IC, color=c, lw=2.0, label=f'I_B={I_B*1e6:.0f} uA')
ax.set_xlabel('V_CE (V)', color='#9ca3af')
ax.set_ylabel('I_C (mA)', color='#9ca3af')
ax.set_title('NPN BJT Collector Curves', color='#d1d5db', pad=8)
ax.tick_params(colors='#9ca3af')
ax.legend(fontsize=7, facecolor='#1f2937', edgecolor='#374151', labelcolor='#d1d5db')
ax.grid(True, color='#1f2937', alpha=0.8)

# Plot 2: NMOS output characteristics
ax = axes[1]
for V_GS, c in zip(V_GS_vals, colors_mos):
    ID = nmos_id(V_DS, V_GS) * 1000   # mA
    ax.plot(V_DS, ID, color=c, lw=2.0, label=f'V_GS={V_GS:.1f}V')
    # Mark triode/saturation boundary
    Vov = V_GS - V_th
    if Vov > 0:
        ax.axvline(Vov, color=c, lw=0.6, ls=':', alpha=0.5)
ax.set_xlabel('V_DS (V)', color='#9ca3af')
ax.set_ylabel('I_D (mA)', color='#9ca3af')
ax.set_title('NMOS Output Characteristics', color='#d1d5db', pad=8)
ax.tick_params(colors='#9ca3af')
ax.legend(fontsize=7, facecolor='#1f2937', edgecolor='#374151', labelcolor='#d1d5db')
ax.grid(True, color='#1f2937', alpha=0.8)

# Plot 3: CMOS inverter transfer curve
ax = axes[2]
ax.plot(V_in, V_out, color='#34d399', lw=2.5)
ax.axvline(VM, color='#fbbf24', ls='--', lw=1.5, label=f'VM = {VM:.2f} V')
ax.axhline(VDD/2, color='#f87171', ls=':', lw=1.2, label=f'VDD/2 = {VDD/2:.1f} V')
ax.plot([0, VDD], [VDD, 0], color='#6b7280', lw=0.8, ls=':', alpha=0.5, label='Ideal (45 deg)')
ax.set_xlabel('V_in (V)', color='#9ca3af')
ax.set_ylabel('V_out (V)', color='#9ca3af')
ax.set_title('CMOS Inverter Transfer Curve', color='#d1d5db', pad=8)
ax.tick_params(colors='#9ca3af')
ax.legend(fontsize=8, facecolor='#1f2937', edgecolor='#374151', labelcolor='#d1d5db')
ax.grid(True, color='#1f2937', alpha=0.8)
ax.set_xlim(0, VDD)
ax.set_ylim(0, VDD)

plt.tight_layout(pad=2.0)
plt.savefig('output.png', dpi=140, bbox_inches='tight', facecolor='#0a0a0a')
print()
print('Plot saved to output.png')

Click Run to execute the Python code

Code will be executed with Python 3 on the server

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