FPGA Design from Scratch · Before the FPGA

Part I: Digital Foundations

Binary numbers, Boolean logic, the combinational building blocks, and the clocked flip-flop. Everything an FPGA is made of, starting from nothing.

The big picture

Every digital system, from a pocket calculator to the Zynq-7020 on the PYNQ-Z2, is made of two kinds of parts: combinational logic, which computes outputs from inputs, and flip-flops, which remember values from one clock tick to the next. Part I builds both from the ground up: the bits and numbers they carry, the gates and blocks that compute, and the clocked memory that turns a pile of gates into a machine that steps through time.

inputsbits, wordscombinational logicgates, MUX, decoder,comparator, adderChapters 1–2next stateregistersD flip-flopsChapter 3outputse.g. LEDspresent state (feedback through the registers)clkone clock, 125 MHz on the PYNQ-Z2
The shape of every synchronous digital design: registers (flip-flops) hold the state, combinational logic computes the next state between clock edges, and one clock updates all registers at once. Chapter 1 supplies the bits and gates, Chapter 2 the logic blocks, Chapter 3 the registers and the clock.

What you will learn, and why it matters for FPGAs

  • Bits and numbers (Chapter 1). Why hardware uses two voltage levels, binary and hexadecimal, and two's complement, the representation of negative numbers that every adder in the FPGA uses. Gates, truth tables, Boolean algebra and De Morgan's laws give you the vocabulary to read any schematic or HDL expression.
  • Combinational building blocks (Chapter 2). Multiplexers, decoders, comparators and adders, derived from their truth tables, plus Karnaugh maps and propagation delay. The multiplexer is the key to understanding the FPGA's look-up table, and the ripple-carry adder explains why FPGAs contain dedicated carry chains.
  • Sequential logic and the clock (Chapter 3). Latches, flip-flops, registers, counters and shift registers, and the synchronous design style with a single clock. The setup-time inequality introduced there is the rule that decides how fast every FPGA design can run.
Why start here
An FPGA is, quite literally, a large array of small look-up tables (which implement truth tables), flip-flops, and programmable wires. Part II opens the chip and finds exactly the elements built in Part I. The HDL code of Part III describes them. Readers who already know digital logic can skim Part I and use its problem sets as a check.

Chapters in Part I

1

Bits, Numbers & Boolean Logic

Why digital means two levels, binary and hexadecimal, two’s complement, logic gates, truth tables and De Morgan’s laws.

BinaryTwo’s complementGatesDe Morgan
2

Combinational Building Blocks

Multiplexers, decoders, comparators, half and full adders, ripple-carry adders, and simplifying logic with Karnaugh maps.

MUXDecoderFull adderK-map
3

Sequential Logic & the Clock

Latches, D flip-flops, registers, counters and shift registers; why synchronous design uses one clock edge; a first look at setup and hold.

D flip-flopRegisterCounterSynchronous
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