Part III: Hardware Description Languages
Describing circuits, not programs. Every construct is shown in both Verilog and VHDL so you can read either and choose one.
From text to silicon
A hardware description language is a way of writing down a circuit as text. Two programs read that text. A simulator runs it on your PC so you can watch the signals over time and check them with a testbench. A synthesiser turns it into a netlist, a list of FPGA primitives (LUTs, flip-flops, carry chains, block RAMs, DSP slices) and the wires between them. Implementation then places each primitive on a specific site of the chip and routes the wires, and the result is packed into a bitstream that configures the FPGA. The three chapters of this part teach the language; Part IV covers simulation in depth, and Part V the rest of the flow on the PYNQ-Z2.
Verilog and VHDL: a fair comparison
Verilog was created in 1984 at Gateway Design Automation as the language of a commercial simulator. After Cadence acquired Gateway, it opened the language, which was standardised as IEEE 1364 in 1995 (major revision 1364-2001). In 2009 it was merged into SystemVerilog(IEEE 1800), which adds many verification features and some convenient design ones. VHDL (VHSIC Hardware Description Language) came out of the US Department of Defense's VHSIC programme in the early 1980s, initially as a way to document the behaviour of the chips contractors delivered. It was standardised as IEEE 1076 in 1987, revised in 1993 and 2008 (and again in 2019). Both languages were designed for simulation first; synthesis tools later adopted a subset of each.
| Verilog | VHDL | |
|---|---|---|
| Origin | 1984, Gateway Design Automation | 1980s, US DoD VHSIC programme |
| Standard | IEEE 1364 (now part of IEEE 1800) | IEEE 1076 (-1987, -1993, -2008, -2019) |
| Style | terse, C-like, case-sensitive | verbose, Ada-like, case-insensitive |
| Typing | weak: bits and numbers mix freely | strong: explicit conversions required |
| Typical mistakes | silent width truncation, signed/unsigned mixing | verbose conversions, sensitivity lists |
| Common in | US industry, ASIC design, open-source tools | Europe, aerospace & defence, FPGA teams |
Neither language is better in any absolute sense. Verilog lets you write less, and it lets you make some mistakes without noticing. VHDL makes you write more, and its type checker catches many of those mistakes before you simulate. Vivado accepts both and mixes them freely in one project, and the synthesised hardware is the same. Who uses which depends mostly on habit, region and industry, and many companies use both.
Chapters in Part III
Thinking in Hardware
Why HDL code is not software: concurrency, synthesis versus simulation, modules and entities, ports and signals, your first design in both languages.
Combinational Logic in HDL
Continuous assignment, always @(*) and VHDL processes, if and case, vectors and arithmetic, and the accidental latch — the classic beginner bug.
Sequential Logic in HDL
Clocked always blocks and rising_edge, blocking versus non-blocking assignment, reset styles, counters, shift registers and parameters/generics.