Part V: From Code to Bitstream
Vivado, constraint files, synthesis, place and route, and the bitstream. First lights on the PYNQ-Z2, then timing closure and crossing clock domains safely.
From a text file to a configured chip
In Parts I–IV every design lived in a simulator. Part V takes the same HDL onto the PYNQ-Z2. Two files go in: your Verilog or VHDL, which says what the circuit does, and an XDC constraint file, which says where its ports are on the package and how fast its clock runs. Vivado then turns them into a bitstream in a fixed sequence of steps, each producing reports you learn to read.
The three chapters follow that path. Chapter 13 tours the board, installs Vivado, explains the XDC file line by line and scripts the whole flow in Tcl. Chapter 14 builds the first real design — a light chaser and a debounced press counter — and programs the board. Chapter 15 opens the timing report: setup and hold, slack and maximum frequency, pipelining, metastability, and how to pass signals safely between clocks.
Chapters in Part V
Vivado & the PYNQ-Z2
Installing Vivado, the PYNQ-Z2 board and its parts, creating a project, the XDC constraint file, and the flow from synthesis to bitstream.
First Lights: LEDs, Buttons & Switches
Blinky from a 125 MHz clock, counters as clock dividers, synchronising and debouncing buttons, and programming the board for the first time.
Timing Closure
Setup and hold, slack and the critical path, maximum clock frequency, pipelining, metastability and its MTBF, and clock domain crossing.