Part VI: Real Designs

Part V put a first design on the PYNQ-Z2. Part VI builds the three blocks that almost every real FPGA design contains, and they fit together into one data path. A UART (Chapter 16) carries bytes between a PC and the programmable logic over a single wire in each direction. FIFOs built on block RAM (Chapter 17) absorb bursts, so a fast sender and a slower processor need not run in lockstep; with Gray-coded pointers they can even sit on different clocks. A fixed-point FIR filter (Chapter 18) does the arithmetic on DSP slices, and its output is checked bit for bit against a Python model.

Each chapter follows the same discipline as the rest of the course: every block is written in Verilog and VHDL, checked by a self-checking testbench in both simulators, and only then taken to the board. In Part VII the UART link is replaced by the much faster AXI bus between the ARM cores and the fabric, but the FIFOs and the filter can be reused unchanged.