Part IV: Simulation & Verification

Every design in this course is checked in a simulator before it goes anywhere near the board. A testbench drives the design under test (DUT) with stimulus, computes the expected outputs with an independent reference model, and compares the two on every cycle. When something disagrees, a waveform file shows every internal signal so you can find the first wrong value, fix the HDL, and run the loop again in seconds.

A simulation of a few thousand cycles runs in well under a second and shows every signal inside the design. A hardware build of the same design takes minutes of synthesis and place-and-route, and on the board you can only observe the handful of pins wired to LEDs or a logic analyser. Bugs that are obvious in a waveform — an X from a forgotten reset, a counter that wraps one cycle late — can take hours to diagnose on hardware, and some, like a simulation/synthesis mismatch, look like random flakiness there. Chapter 10 builds self-checking testbenches, Chapter 11 teaches you to read waveforms and recognise the common bugs, and Chapter 12 applies both to finite state machines, the control logic of almost every design that follows.