What Is an FPGA?

In Part I you built adders, multiplexers, counters and registers from logic gates and flip-flops. On paper, a circuit is a set of gates plus the wires that connect them. When a company manufactures a chip, both the gates and the wires are fixed forever in the silicon. A field-programmable gate array(FPGA) is different: it is a chip full of small, generic logic elements and a huge network of programmable wires, and you decide — after the chip has left the factory, “in the field” — what each element computes and how they are connected.

The name explains itself. Gate array was an older kind of chip whose transistors were made in advance and whose final metal wiring layers were added to order by the manufacturer. Field-programmablemeans the customization is done by loading a file into the chip, in seconds, as many times as you like. That file is called the bitstream.

It helps to be precise about what an FPGA is not. It is not a processor: it does not fetch and execute instructions (unless you build a processor out of it). When you “program” an FPGA you are not writing a list of steps; you are describing a circuit, and the tools turn that description into the settings of millions of tiny switches. That is why this course talks about hardware description languages (Part III) rather than programming languages.

Recall from Chapter 1 that any Boolean function can be written as a sum of products: an OR of several AND terms, such as \(y = a\,\bar b + \bar a\, c\, d\). The first programmable logic chips of the 1970s were built directly on this fact.

• A PLA (programmable logic array) has a programmable AND array that forms product terms from the inputs and their complements, followed by a programmable OR array that sums them. Flexible, but two layers of programmable connections made it slow and expensive.
• A PAL (programmable array logic, Monolithic Memories, late 1970s) keeps the AND array programmable but fixes the OR gates: each output sums a fixed number of product terms, typically seven or eight. Simpler and faster. PALs were programmed once by blowing tiny fuses.
• A GAL (generic array logic, Lattice, mid-1980s) is an electrically erasable PAL, and its outputs pass through a configurable macrocell that can include a flip-flop. Parts such as the 22V10 are still sold.
• A CPLD (complex programmable logic device) puts dozens of PAL-like blocks on one chip and joins them with a central programmable interconnect. Its configuration lives in on-chip flash or EEPROM, so it works the instant power is applied.

Sum-of-products devices are fast and predictable, but they scale badly. Each output can only use a few product terms, a flip-flop is tied to each output, and making the central AND array bigger makes every signal slower. Something different was needed to build circuits with thousands of gates.

In 1984 Ross Freeman, Bernard Vonderschmitt and James Barnett founded Xilinx around a different idea. Instead of one big AND–OR array, place a regular grid of small, identical logic blocks, surround them with channels of wires, and put programmable switches where the wires cross. Each logic block would compute its function with a look-up table (LUT) — a tiny memory holding the function's truth table — followed by an optional flip-flop. The first product, the XC2064 (1985), had an 8 × 8 grid of 64 such configurable logic blocks, each able to compute any function of up to four inputs (or two functions of three) and to register the result.

Freeman's bet was that transistors would keep getting cheaper (Moore's law), so “wasting” most of a chip on programmability would become affordable. He was right. The XC2064 replaced roughly a thousand gates; the Zynq-7020 on your board has 53,200 six-input LUTs and 106,400 flip-flops, and the largest current devices have millions of LUTs.

The industry grew around a handful of companies: Xilinx (part of AMD since 2022) and Altera (bought by Intel in 2015, now an independent company again) dominate high-end parts; Lattice, Microchip, and newer firms such as Efinix and Gowin make smaller and low-power devices. The vocabulary differs between vendors — Altera says ALM and LAB where Xilinx says slice and CLB — but the architecture is recognisably the same. This course uses Xilinx names because the PYNQ-Z2 carries a Xilinx chip.

How does a chip “become” your circuit? In a modern Xilinx FPGA, every programmable choice is controlled by one bit of configuration memory: static RAM (SRAM) cells scattered all over the die, right next to the thing they control. One bit stores one row of a LUT's truth table. Another bit turns on a pass transistor that joins two routing wires. Others select whether a flip-flop uses a clock enable, what voltage standard an I/O pin uses, and so on.

The bitstream is simply the file containing the value of every one of those cells, plus commands for the chip's configuration controller. Vivado (Chapter 13) produces it as a .bitfile at the end of the design flow. For the Zynq XC7Z020 it is about 32 Mbit (roughly 4 MB), whatever the size of your design: unused resources are configured too, just to “off”.

Because SRAM is volatile, the configuration disappears when power is removed. Every SRAM FPGA therefore has to be configured again at each power-up: from an external flash chip, through the JTAG debug port (what Vivado's Hardware Manager does), or — on the Zynq — by the ARM processor, which can read a bitstream from the SD card and load it into the programmable logic while Linux is running. That last trick is how PYNQ swaps “overlays” in Part VII.

FPGAs compete with three other ways of doing computation. The right choice depends on a handful of properties. A few terms first: latency is the time from an input arriving to its result being ready; throughput is how many results per second come out; NRE(non-recurring engineering) is the one-off cost of designing and manufacturing the first chip.

The FPGA's clock is ten times slower than a CPU's, because programmable wires and LUTs are slower than custom ones. It wins when the algorithm has enough parallelism to keep thousands of small units busy at once, when latency must be short and exactly predictable, or when it must talk directly to unusual hardware (sensors, ADCs, high-speed serial links) with cycle-level timing that software cannot guarantee.

Against an ASIC (application-specific integrated circuit — a chip designed for one job), the FPGA trades performance and unit price for zero mask cost and the ability to fix bugs after shipping. If the total cost of \(N\) units is a fixed NRE plus a per-unit price \(c\), the two routes cost the same at

The program below plots this break-even with illustrative numbers, and compares the idealised throughput of a 64-tap FIR filter (a weighted sum of the last 64 samples, the subject of Chapter 18) on one CPU core and on FPGA fabric with one multiplier per tap.

The FPGA bar is only about three times the SIMD core, despite having 64 multipliers, because it runs at a fifth of the clock. But it is one filter; the XC7Z020 has 220 hardware multipliers (Chapter 6), so three such filters fit side by side, and the latency of each sample stays fixed at a few tens of nanoseconds.

• Prototyping chips. ASIC designers run their design on large FPGA boards before paying for masks, often thousands of times faster than simulation.
• Telecommunications and networking. Mobile base stations, routers and “smart” network cards process packets at line rate, and standards change faster than ASICs can follow.
• Instruments and science. Oscilloscopes, software-defined radios, radio telescopes, and the trigger systems of particle-physics detectors, which must decide in microseconds which collisions to keep.
• Aerospace and defence. Low volumes, long lifetimes, and radiation-tolerant parts.
• Finance. Trading systems where shaving a microsecond of latency is worth money.
• Data centres. Accelerators for search, compression, encryption and machine-learning inference.
• Industrial control, video and embedded vision. Motor control, camera pipelines, machine vision — exactly the niche of the Zynq.
• Hobby and education. Retro-computer recreations and courses like this one.

In space, radiation can flip a configuration bit (a single-event upset), silently changing the circuit. A classic defence is triple modular redundancy: build the circuit three times and take a bitwise majority vote, so a single faulty copy is outvoted. The voter is a good first look at the HDL you will write from Part III onward — do not worry about the syntax yet; notice only that it describes a circuit, not a sequence of steps.

// Bitwise 2-out-of-3 majority voter, as used in triple modular redundancy (TMR)
module vote3 #(
    parameter WIDTH = 8
) (
    input  wire [WIDTH-1:0] a,
    input  wire [WIDTH-1:0] b,
    input  wire [WIDTH-1:0] c,
    output wire [WIDTH-1:0] y
);
    // Each output bit is 1 when at least two of the three copies say 1
    assign y = (a & b) | (a & c) | (b & c);
endmodule

-- Bitwise 2-out-of-3 majority voter, as used in triple modular redundancy (TMR)
library ieee;
use ieee.std_logic_1164.all;

entity vote3 is
    generic (
        WIDTH : positive := 8
    );
    port (
        a : in  std_logic_vector(WIDTH - 1 downto 0);
        b : in  std_logic_vector(WIDTH - 1 downto 0);
        c : in  std_logic_vector(WIDTH - 1 downto 0);
        y : out std_logic_vector(WIDTH - 1 downto 0)
    );
end entity;

architecture rtl of vote3 is
begin
    -- Each output bit is 1 when at least two of the three copies say 1
    y <= (a and b) or (a and c) or (b and c);
end architecture;

Each output bit depends on exactly three inputs, so the synthesiser maps each bit to one look-up table: eight LUTs for the default width of 8. A testbench (Chapter 10) applies all 4,096 combinations of three 4-bit inputs and compares against a direct count of ones; both languages print PASS: 4096 input combinations, 0 errors.

`timescale 1ns / 1ps
module vote3_tb;
    reg  [3:0] a, b, c;
    wire [3:0] y;
    reg  [3:0] expected;
    integer i, k, ones, errors;

    vote3 #(.WIDTH(4)) dut (.a(a), .b(b), .c(c), .y(y));

    initial begin
        errors = 0;
        for (i = 0; i < 4096; i = i + 1) begin   // every combination of 3 x 4 bits
            {a, b, c} = i;
            #1;
            for (k = 0; k < 4; k = k + 1) begin
                ones = a[k] + b[k] + c[k];
                expected[k] = (ones >= 2);
            end
            if (y !== expected) errors = errors + 1;
        end
        if (errors == 0)
            $display("PASS: 4096 input combinations, 0 errors");
        else
            $display("FAIL: %0d errors", errors);
        $finish;
    end
endmodule

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vote3_tb is
end entity;

architecture sim of vote3_tb is
    signal a, b, c, y : std_logic_vector(3 downto 0);
begin
    dut : entity work.vote3
        generic map (WIDTH => 4)
        port map (a => a, b => b, c => c, y => y);

    stimulus : process
        variable v        : std_logic_vector(11 downto 0);
        variable expected : std_logic_vector(3 downto 0);
        variable ones     : natural;
        variable errors   : natural := 0;
    begin
        for i in 0 to 4095 loop                 -- every combination of 3 x 4 bits
            v := std_logic_vector(to_unsigned(i, 12));
            a <= v(11 downto 8);
            b <= v(7 downto 4);
            c <= v(3 downto 0);
            wait for 1 ns;
            for k in 0 to 3 loop
                ones := 0;
                if a(k) = '1' then ones := ones + 1; end if;
                if b(k) = '1' then ones := ones + 1; end if;
                if c(k) = '1' then ones := ones + 1; end if;
                if ones >= 2 then expected(k) := '1'; else expected(k) := '0'; end if;
            end loop;
            if y /= expected then errors := errors + 1; end if;
        end loop;
        if errors = 0 then
            report "PASS: 4096 input combinations, 0 errors";
        else
            report "FAIL: " & integer'image(errors) & " errors" severity error;
        end if;
        wait;
    end process;
end architecture;

The chip on your board, the XC7Z020-1CLG400C, is not a plain FPGA. It belongs to the Zynq-7000 family, a system-on-chip (SoC) that combines two worlds on one die:

• the processing system (PS): a dual-core ARM Cortex-A9 (650 MHz on this board) with caches, a DDR3 memory controller (512 MB on the board), USB, Ethernet, SD card and UART controllers. This is a complete computer; the PYNQ image runs Linux and Jupyter on it.
• the programmable logic (PL): an FPGA fabric of the Xilinx 7-series (similar to an Artix-7) with 53,200 LUTs, 106,400 flip-flops, 140 block RAMs of 36 Kb and 220 DSP48E1 multiply–accumulate slices.

The part number itself is a small data sheet:

Parts II to VI use only the PL: you design a circuit, load it through JTAG, and watch LEDs and pins. Part VII brings the PS in, connecting your circuits to software through the AXI bus. Chapters 5 and 6 now open up the PL and look at what those 53,200 LUTs and 220 DSP slices actually are.

LUTs (6-input)        53,200    -> Chapter 5
Flip-flops           106,400    -> Chapter 5
Block RAM (36 Kb)        140    -> Chapter 6   (4.9 Mb total)
DSP48E1 slices           220    -> Chapter 6
Processor (PS)   2 x Cortex-A9  -> Chapter 6 (intro), Part VII

A short checklist, in rough order of importance:

1. Is there parallelism or streaming? Data that flows continuously (samples, pixels, packets) through a fixed sequence of operations is ideal. Branchy, pointer-chasing code is not.
2. Do you need deterministic timing? Nanosecond-exact responses, precise pulse generation, or custom interfaces point to an FPGA.
3. Is the volume moderate and the specification still moving? Then an ASIC is too expensive and too rigid.
4. Is a CPU or GPU fast enough? If so, use it: software is far cheaper to write, debug and maintain.