Memories & FIFOs

Inferring ROM and block RAM from HDL, initialising memories from files, synchronous FIFOs with full and empty flags, and Gray-code pointers.

1. A memory is an array of registers

Every design so far stored its data in a handful of flip-flops. As soon as you need to keep hundreds or thousands of values — a lookup table, a line of an image, bytes waiting to be sent over the UART of Chapter 16 — you need a memory: an array of words, each selected by an address.

In HDL a memory is simply a two-dimensional array. In Verilog reg [7:0] mem [0:1023] declares 1024 words of 8 bits; in VHDL you first declare an array type and then a signal of that type. Writing is always done on a clock edge. The interesting question is how you read it, because that decides what hardware the synthesiser builds:

Read style	HDL	Hardware chosen by Vivado	Typical size
constant, combinational	case / constant array	LUTs (logic)	a few dozen words
asynchronous (no clock)	assign dout = mem[addr]	distributed RAM (LUT RAM)	≤ ~256 words
synchronous (registered)	dout <= mem[addr] in a clocked block	block RAM (BRAM)	hundreds to many thousands

Chapter 6 introduced the hardware: the XC7Z020 has 140 block RAMs of 36 Kb each — 4.9 Mb in total — as dedicated memory blocks on the die. Each one has registered inputs (address, data, enables) plus an optional output register, which is why it can only be read synchronously: the address is captured on a clock edge and the data appears after it.

2. Read-only memories

A ROM (read-only memory) is a fixed table: an address goes in, a stored value comes out. The smallest ROMs are just case statements. Here is the classic one, the decoder for a seven-segment display. It is 16 words of 7 bits, and the synthesiser turns it into a few LUTs (each LUT is itself a tiny ROM, Chapter 5).

hex7seg — a ROM written as a case statement

Verilog

module hex7seg (
    input  wire [3:0] digit,
    output reg  [6:0] seg        // segments g..a, 1 = lit
);
    // A 16-word x 7-bit ROM written as a case statement
    always @(*) begin
        case (digit)
            4'h0: seg = 7'b0111111;
            4'h1: seg = 7'b0000110;
            4'h2: seg = 7'b1011011;
            4'h3: seg = 7'b1001111;
            4'h4: seg = 7'b1100110;
            4'h5: seg = 7'b1101101;
            4'h6: seg = 7'b1111101;
            4'h7: seg = 7'b0000111;
            4'h8: seg = 7'b1111111;
            4'h9: seg = 7'b1101111;
            4'hA: seg = 7'b1110111;
            4'hB: seg = 7'b1111100;
            4'hC: seg = 7'b0111001;
            4'hD: seg = 7'b1011110;
            4'hE: seg = 7'b1111001;
            default: seg = 7'b1110001;   // F
        endcase
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity hex7seg is
    port (
        digit : in  std_logic_vector(3 downto 0);
        seg   : out std_logic_vector(6 downto 0)   -- segments g..a, 1 = lit
    );
end entity;

architecture rtl of hex7seg is
begin
    -- A 16-word x 7-bit ROM written as a case statement
    process (digit)
    begin
        case digit is
            when x"0"   => seg <= "0111111";
            when x"1"   => seg <= "0000110";
            when x"2"   => seg <= "1011011";
            when x"3"   => seg <= "1001111";
            when x"4"   => seg <= "1100110";
            when x"5"   => seg <= "1101101";
            when x"6"   => seg <= "1111101";
            when x"7"   => seg <= "0000111";
            when x"8"   => seg <= "1111111";
            when x"9"   => seg <= "1101111";
            when x"A"   => seg <= "1110111";
            when x"B"   => seg <= "1111100";
            when x"C"   => seg <= "0111001";
            when x"D"   => seg <= "1011110";
            when x"E"   => seg <= "1111001";
            when others => seg <= "1110001";   -- F
        end case;
    end process;
end architecture;

For larger tables, writing a case per entry is impractical. Verilog can load the array from a text file at the start of simulation and synthesis with $readmemh (hexadecimal values, one per line; $readmemb reads binary). Vivado honours it and puts the values into the bitstream. In VHDL the portable way that also works in VHDL-93 is a constant array written out in the source; a short script (like the one that produced sine64.hex) can generate both. The VHDL file can also be read with the textio package in a function, but that is more code and depends on the tool, so we stay with the constant.

sine_rom — 64-sample sine table with a synchronous read

Verilog

module sine_rom (
    input  wire       clk,
    input  wire [5:0] addr,       // 64 samples per period
    output reg  [7:0] dout = 8'd0 // unsigned, 0x80 = zero crossing
);
    reg [7:0] rom [0:63];

    // Contents come from a text file: one hex value per line
    initial $readmemh("sine64.hex", rom);

    always @(posedge clk)
        dout <= rom[addr];        // synchronous read -> block RAM
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sine_rom is
    port (
        clk  : in  std_logic;
        addr : in  std_logic_vector(5 downto 0);   -- 64 samples per period
        dout : out std_logic_vector(7 downto 0)    -- unsigned, x"80" = zero
    );
end entity;

architecture rtl of sine_rom is
    type rom_t is array (0 to 63) of std_logic_vector(7 downto 0);
    -- Contents as a constant: same values as sine64.hex
    constant ROM : rom_t := (
        x"80", x"8C", x"98", x"A5", x"B0", x"BC", x"C6", x"D0",
        x"DA", x"E2", x"EA", x"F0", x"F5", x"FA", x"FD", x"FE",
        x"FF", x"FE", x"FD", x"FA", x"F5", x"F0", x"EA", x"E2",
        x"DA", x"D0", x"C6", x"BC", x"B0", x"A5", x"98", x"8C",
        x"80", x"73", x"67", x"5A", x"4F", x"43", x"39", x"2F",
        x"25", x"1D", x"15", x"0F", x"0A", x"05", x"02", x"01",
        x"00", x"01", x"02", x"05", x"0A", x"0F", x"15", x"1D",
        x"25", x"2F", x"39", x"43", x"4F", x"5A", x"67", x"73");
    signal dout_r : std_logic_vector(7 downto 0) := (others => '0');
begin
    process (clk)
    begin
        if rising_edge(clk) then
            dout_r <= ROM(to_integer(unsigned(addr)));  -- synchronous read
        end if;
    end process;
    dout <= dout_r;
end architecture;

sine64.hex (first 8 of 64 lines)

80
8C
98
A5
B0
BC
C6
D0

rom_tb — checks the decoder and five sine samples

Verilog

`timescale 1ns/1ps
module rom_tb;
    reg        clk = 0;
    reg  [3:0] digit = 4'h0;
    reg  [5:0] addr = 6'd0;
    wire [6:0] seg;
    wire [7:0] sample;
    integer errors = 0;

    hex7seg  u_seg (.digit(digit), .seg(seg));
    sine_rom u_sin (.clk(clk), .addr(addr), .dout(sample));

    always #4 clk = ~clk;

    task check_sine(input [5:0] a, input [7:0] expected);
        begin
            addr = a;
            @(posedge clk); #1;                 // data appears after the edge
            if (sample !== expected) begin
                $display("FAIL: sine[%0d] = %h, expected %h", a, sample, expected);
                errors = errors + 1;
            end
        end
    endtask

    initial begin
        digit = 4'h8; #1;
        if (seg !== 7'b1111111) begin $display("FAIL: 8 -> %b", seg); errors = errors + 1; end
        digit = 4'h1; #1;
        if (seg !== 7'b0000110) begin $display("FAIL: 1 -> %b", seg); errors = errors + 1; end
        check_sine(0, 8'h80);  check_sine(16, 8'hFF);
        check_sine(32, 8'h80); check_sine(48, 8'h00); check_sine(5, 8'hBC);
        if (errors == 0) $display("PASS: ROM contents as expected");
        $finish;
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rom_tb is
end entity;

architecture sim of rom_tb is
    signal clk    : std_logic := '0';
    signal digit  : std_logic_vector(3 downto 0) := x"0";
    signal addr   : std_logic_vector(5 downto 0) := (others => '0');
    signal seg    : std_logic_vector(6 downto 0);
    signal sample : std_logic_vector(7 downto 0);
    signal done   : boolean := false;
begin
    u_seg : entity work.hex7seg port map (digit => digit, seg => seg);
    u_sin : entity work.sine_rom port map (clk => clk, addr => addr, dout => sample);

    clk <= not clk after 4 ns when not done;

    process
        variable errors : natural := 0;
        procedure check_sine(a : natural; expected : std_logic_vector(7 downto 0)) is
        begin
            addr <= std_logic_vector(to_unsigned(a, 6));
            wait until rising_edge(clk); wait for 1 ns;   -- data after the edge
            if sample /= expected then
                report "FAIL: sine[" & integer'image(a) & "] = " & to_hstring(sample);
                errors := errors + 1;
            end if;
        end procedure;
    begin
        digit <= x"8"; wait for 1 ns;
        if seg /= "1111111" then report "FAIL: 8"; errors := errors + 1; end if;
        digit <= x"1"; wait for 1 ns;
        if seg /= "0000110" then report "FAIL: 1"; errors := errors + 1; end if;
        check_sine(0, x"80");  check_sine(16, x"FF");
        check_sine(32, x"80"); check_sine(48, x"00"); check_sine(5, x"BC");
        if errors = 0 then report "PASS: ROM contents as expected"; end if;
        done <= true;
        wait;
    end process;
end architecture;

Both simulators print PASS: ROM contents as expected at 37 ns. Notice in the testbench that the sine value is checked after the clock edge: a synchronous ROM has one cycle of latency.

3. RAM templates that Vivado recognises

Synthesis tools recognise memories by pattern. If your code matches the pattern, you get a block RAM for free; if it does not, you may get thousands of flip-flops and multiplexers instead. The rule for block RAM is: write and read inside a clocked process, and register the read data.

ram_sp — single-port block RAM (one address for read and write)

Verilog

module ram_sp #(
    parameter DW = 16,               // data width
    parameter AW = 10                // address width: 2**AW words
) (
    input  wire          clk,
    input  wire          we,         // write enable
    input  wire [AW-1:0] addr,
    input  wire [DW-1:0] din,
    output reg  [DW-1:0] dout = 0
);
    reg [DW-1:0] mem [0:(1<<AW)-1];

    always @(posedge clk) begin
        if (we)
            mem[addr] <= din;
        dout <= mem[addr];           // registered read: old data (read-first)
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_sp is
    generic (
        DW : positive := 16;             -- data width
        AW : positive := 10              -- address width: 2**AW words
    );
    port (
        clk  : in  std_logic;
        we   : in  std_logic;            -- write enable
        addr : in  std_logic_vector(AW-1 downto 0);
        din  : in  std_logic_vector(DW-1 downto 0);
        dout : out std_logic_vector(DW-1 downto 0)
    );
end entity;

architecture rtl of ram_sp is
    type mem_t is array (0 to 2**AW - 1) of std_logic_vector(DW-1 downto 0);
    signal mem    : mem_t;
    signal dout_r : std_logic_vector(DW-1 downto 0) := (others => '0');
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                mem(to_integer(unsigned(addr))) <= din;
            end if;
            dout_r <= mem(to_integer(unsigned(addr)));  -- old data (read-first)
        end if;
    end process;
    dout <= dout_r;
end architecture;

When you write and read the same address in the same cycle, this template returns the old contents (“read-first”), because the read uses the value of mem before the edge. Block RAMs support this mode natively, as well as “write-first” and “no-change”.

Most designs need to write at one address while reading another — a FIFO is the obvious example. Block RAMs have two independent ports, so the simple dual-port template, with one write port and one read port, maps onto a single block:

ram_sdp — simple dual-port block RAM (write port A, read port B)

Verilog

module ram_sdp #(
    parameter DW = 16,
    parameter AW = 10
) (
    input  wire          clk,
    // write port A
    input  wire          we,
    input  wire [AW-1:0] waddr,
    input  wire [DW-1:0] din,
    // read port B
    input  wire          re,          // read enable
    input  wire [AW-1:0] raddr,
    output reg  [DW-1:0] dout = 0
);
    reg [DW-1:0] mem [0:(1<<AW)-1];

    always @(posedge clk) begin
        if (we)
            mem[waddr] <= din;
        if (re)
            dout <= mem[raddr];       // synchronous read on its own address
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_sdp is
    generic (
        DW : positive := 16;
        AW : positive := 10
    );
    port (
        clk   : in  std_logic;
        -- write port A
        we    : in  std_logic;
        waddr : in  std_logic_vector(AW-1 downto 0);
        din   : in  std_logic_vector(DW-1 downto 0);
        -- read port B
        re    : in  std_logic;            -- read enable
        raddr : in  std_logic_vector(AW-1 downto 0);
        dout  : out std_logic_vector(DW-1 downto 0)
    );
end entity;

architecture rtl of ram_sdp is
    type mem_t is array (0 to 2**AW - 1) of std_logic_vector(DW-1 downto 0);
    signal mem    : mem_t;
    signal dout_r : std_logic_vector(DW-1 downto 0) := (others => '0');
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                mem(to_integer(unsigned(waddr))) <= din;
            end if;
            if re = '1' then
                dout_r <= mem(to_integer(unsigned(raddr)));  -- synchronous read
            end if;
        end if;
    end process;
    dout <= dout_r;
end architecture;

If you read asynchronously — data available in the same cycle, no clock — the block RAM cannot be used. Vivado then builds distributed RAM out of LUTs: in some slices, a 6-input LUT can act as a 64 × 1-bit RAM. That is ideal for small memories such as register files, and wasteful for large ones.

ram_dist — distributed (LUT) RAM: synchronous write, asynchronous read

Verilog

module ram_dist #(
    parameter DW = 8,
    parameter AW = 5                  // 32 words: small, LUT-based
) (
    input  wire          clk,
    input  wire          we,
    input  wire [AW-1:0] addr,
    input  wire [DW-1:0] din,
    output wire [DW-1:0] dout
);
    reg [DW-1:0] mem [0:(1<<AW)-1];

    always @(posedge clk)
        if (we)
            mem[addr] <= din;         // write is synchronous

    assign dout = mem[addr];          // read is asynchronous -> LUT RAM
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram_dist is
    generic (
        DW : positive := 8;
        AW : positive := 5                -- 32 words: small, LUT-based
    );
    port (
        clk  : in  std_logic;
        we   : in  std_logic;
        addr : in  std_logic_vector(AW-1 downto 0);
        din  : in  std_logic_vector(DW-1 downto 0);
        dout : out std_logic_vector(DW-1 downto 0)
    );
end entity;

architecture rtl of ram_dist is
    type mem_t is array (0 to 2**AW - 1) of std_logic_vector(DW-1 downto 0);
    signal mem : mem_t;
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                mem(to_integer(unsigned(addr))) <= din;  -- synchronous write
            end if;
        end if;
    end process;
    dout <= mem(to_integer(unsigned(addr)));             -- asynchronous read
end architecture;

Common mistake: a reset on the memory array

Putting the memory array inside an if (rst) branch that clears all words (a for loop over every address) cannot be mapped to block RAM, which has no way to clear all its contents in one cycle. Vivado falls back to flip-flops — 16 384 of them for a 1K × 16 memory. Reset the pointers and control logic around a memory, never the memory itself. Initial contents (from a file or constant) are fine: they are loaded with the bitstream.

4. Sizing memories in block RAM units

A 36 Kb block RAM (36 864 bits, including one parity bit per byte that can store data) can be configured with different aspect ratios — the product of depth and width is roughly constant. It can also be split into two independent 18 Kb halves.

Configuration (one 36 Kb block)	Depth × width
deep and narrow	32K × 1, 16K × 2, 8K × 4
with parity bits used as data	4K × 9, 2K × 18, 1K × 36
simple dual-port only (widest)	512 × 72

Vivado tiles a larger memory with several blocks. A quick estimate for the number of 36 Kb blocks is

\[ N_\text{BRAM} \;\gtrsim\; \left\lceil \frac{\text{depth} \times \text{width}}{36\,864} \right\rceil \]

but the real count depends on the aspect ratio. A 4096 × 32 memory holds 131 072 bits, so the estimate gives 4; using four 4K × 9 blocks side by side indeed gives 4K × 36 and wastes 4 bits per word. A 4096 × 8 memory fits one block exactly. Always check the utilization report after synthesis for the actual number of RAMB36/RAMB18 used.

5. The synchronous FIFO

A FIFO (first in, first out) is a queue. One side writes words when it has them; the other side reads them, in the same order, when it is ready. It decouples a producer from a consumer that do not work in lockstep — exactly what was missing in the UART echo of Chapter 16.

Inside, a FIFO is a dual-port RAM used as a circular buffer with two counters: the write pointer (where the next word goes) and the read pointer (where the next word comes from). Both only count up and wrap around at the end of the memory. The difficulty is the flags: if both pointers are equal, is the FIFO empty (the reader caught up) or full (the writer went round once and caught up from behind)?

A 4-word FIFO with pointers one bit wider than the address. The low bits select the RAM word; the top bit counts laps. Equal pointers mean empty; same address on different laps means full.

The elegant solution is to make each pointer one bit wider than the address. The low bits address the RAM; the extra top bit flips every time the pointer completes a lap. Then:

\[ \text{empty} \iff w = r, \qquad \text{full} \iff w_\text{low} = r_\text{low} \;\wedge\; w_\text{top} \neq r_\text{top}, \qquad \text{count} = (w - r) \bmod 2^{A+1} \]

fifo_sync — single-clock FIFO with block-RAM storage

Verilog

module fifo_sync #(
    parameter DW = 8,                 // data width
    parameter AW = 4                  // depth = 2**AW words
) (
    input  wire          clk,
    input  wire          rst,
    // write side
    input  wire          wr_en,
    input  wire [DW-1:0] din,
    output wire          full,
    // read side
    input  wire          rd_en,
    output reg  [DW-1:0] dout = 0,    // valid the cycle after rd_en
    output wire          empty,
    output wire [AW:0]   count        // words stored, 0 .. 2**AW
);
    reg [DW-1:0] mem [0:(1<<AW)-1];
    reg [AW:0]   wptr = 0, rptr = 0;  // one extra bit: the "lap" bit

    wire do_wr = wr_en && !full;      // refuse writes when full
    wire do_rd = rd_en && !empty;     // refuse reads when empty

    always @(posedge clk) begin
        if (do_wr)
            mem[wptr[AW-1:0]] <= din;
        if (do_rd)
            dout <= mem[rptr[AW-1:0]];  // synchronous read -> block RAM
    end

    always @(posedge clk) begin
        if (rst) begin
            wptr <= 0;
            rptr <= 0;
        end else begin
            if (do_wr) wptr <= wptr + 1'b1;
            if (do_rd) rptr <= rptr + 1'b1;
        end
    end

    // Same address, same lap -> empty. Same address, different lap -> full.
    assign empty = (wptr == rptr);
    assign full  = (wptr[AW-1:0] == rptr[AW-1:0]) && (wptr[AW] != rptr[AW]);
    assign count = wptr - rptr;
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fifo_sync is
    generic (
        DW : positive := 8;               -- data width
        AW : positive := 4                -- depth = 2**AW words
    );
    port (
        clk   : in  std_logic;
        rst   : in  std_logic;
        -- write side
        wr_en : in  std_logic;
        din   : in  std_logic_vector(DW-1 downto 0);
        full  : out std_logic;
        -- read side
        rd_en : in  std_logic;
        dout  : out std_logic_vector(DW-1 downto 0);  -- valid after rd_en
        empty : out std_logic;
        count : out std_logic_vector(AW downto 0)     -- words stored
    );
end entity;

architecture rtl of fifo_sync is
    type mem_t is array (0 to 2**AW - 1) of std_logic_vector(DW-1 downto 0);
    signal mem    : mem_t;
    signal wptr   : unsigned(AW downto 0) := (others => '0');  -- extra lap bit
    signal rptr   : unsigned(AW downto 0) := (others => '0');
    signal dout_r : std_logic_vector(DW-1 downto 0) := (others => '0');
    signal full_i, empty_i, do_wr, do_rd : std_logic;
begin
    do_wr <= wr_en and not full_i;        -- refuse writes when full
    do_rd <= rd_en and not empty_i;       -- refuse reads when empty

    process (clk)
    begin
        if rising_edge(clk) then
            if do_wr = '1' then
                mem(to_integer(wptr(AW-1 downto 0))) <= din;
            end if;
            if do_rd = '1' then
                dout_r <= mem(to_integer(rptr(AW-1 downto 0)));  -- sync read
            end if;
        end if;
    end process;

    process (clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                wptr <= (others => '0');
                rptr <= (others => '0');
            else
                if do_wr = '1' then wptr <= wptr + 1; end if;
                if do_rd = '1' then rptr <= rptr + 1; end if;
            end if;
        end if;
    end process;

    -- Same address, same lap -> empty. Same address, different lap -> full.
    empty_i <= '1' when wptr = rptr else '0';
    full_i  <= '1' when wptr(AW-1 downto 0) = rptr(AW-1 downto 0)
                    and wptr(AW) /= rptr(AW) else '0';
    full  <= full_i;
    empty <= empty_i;
    count <= std_logic_vector(wptr - rptr);
    dout  <= dout_r;
end architecture;

The FIFO protects itself: a write while full (overflow) and a read while empty (underflow) are simply ignored. Like the block RAM it is built on, dout appears one cycle after rd_en. This style is called a “standard” FIFO; a “first-word fall-through” FIFO instead shows the next word on dout before it is read, at the cost of an extra output register and some logic.

Key idea: depth is a power of two

With depth $2^A$, pointers simply wrap by overflowing their binary counter, and the extra-bit trick works with no comparisons against a maximum. That is why FIFO depths are almost always 16, 512, 1024…

6. Testing the FIFO, including abuse

A good FIFO testbench does not only check the happy path. This one uses a 4-word FIFO and tries to write 6 words (two must be refused), reads 6 times (two must be refused, and dout must keep its last value), and finally reads and writes in the same cycle.

fifo_sync_tb — overflow, underflow and simultaneous access

Verilog

`timescale 1ns/1ps
module fifo_sync_tb;
    reg        clk = 0, rst = 0, wr_en = 0, rd_en = 0;
    reg  [7:0] din = 8'd0;
    wire [7:0] dout;
    wire       full, empty;
    wire [2:0] count;
    integer i, errors = 0;

    fifo_sync #(.DW(8), .AW(2)) dut (      // depth 4, so it fills quickly
        .clk(clk), .rst(rst), .wr_en(wr_en), .din(din), .full(full),
        .rd_en(rd_en), .dout(dout), .empty(empty), .count(count));

    always #4 clk = ~clk;

    task check(input cond, input [8*24-1:0] what);
        if (!cond) begin $display("FAIL: %0s", what); errors = errors + 1; end
    endtask

    initial begin
        @(negedge clk);
        check(empty && !full, "empty after start");
        // 1. Write 6 words into a 4-deep FIFO: the last 2 must be refused
        for (i = 1; i <= 6; i = i + 1) begin
            din = 8'h10 + i; wr_en = 1;
            @(negedge clk);
        end
        wr_en = 0;
        check(full && count == 4, "full with 4 words");
        // 2. Read 6 times: 4 words in order, then 2 refused reads
        for (i = 1; i <= 6; i = i + 1) begin
            rd_en = 1;
            @(negedge clk);
            if (i <= 4) check(dout == 8'h10 + i, "data in order");
        end
        rd_en = 0;
        check(empty && count == 0, "empty after underflow");
        check(dout == 8'h14, "underflow kept dout");
        // 3. Simultaneous read and write with one word stored
        din = 8'hA0; wr_en = 1; @(negedge clk);
        din = 8'hA1; rd_en = 1; @(negedge clk);
        wr_en = 0; rd_en = 0;
        check(dout == 8'hA0 && count == 1, "read+write same cycle");
        if (errors == 0)
            $display("PASS: overflow and underflow refused, order kept, count=%0d", count);
        $finish;
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fifo_sync_tb is
end entity;

architecture sim of fifo_sync_tb is
    signal clk, rst, wr_en, rd_en : std_logic := '0';
    signal din, dout   : std_logic_vector(7 downto 0) := (others => '0');
    signal full, empty : std_logic;
    signal count       : std_logic_vector(2 downto 0);
    signal done        : boolean := false;
begin
    dut : entity work.fifo_sync               -- depth 4, so it fills quickly
        generic map (DW => 8, AW => 2)
        port map (clk => clk, rst => rst, wr_en => wr_en, din => din, full => full,
                  rd_en => rd_en, dout => dout, empty => empty, count => count);

    clk <= not clk after 4 ns when not done;

    process
        variable errors : natural := 0;
        procedure check(cond : boolean; what : string) is
        begin
            if not cond then report "FAIL: " & what; errors := errors + 1; end if;
        end procedure;
    begin
        wait until falling_edge(clk);
        check(empty = '1' and full = '0', "empty after start");
        -- 1. Write 6 words into a 4-deep FIFO: the last 2 must be refused
        for i in 1 to 6 loop
            din <= std_logic_vector(to_unsigned(16#10# + i, 8)); wr_en <= '1';
            wait until falling_edge(clk);
        end loop;
        wr_en <= '0';
        check(full = '1' and unsigned(count) = 4, "full with 4 words");
        -- 2. Read 6 times: 4 words in order, then 2 refused reads
        for i in 1 to 6 loop
            rd_en <= '1';
            wait until falling_edge(clk);
            if i <= 4 then
                check(unsigned(dout) = 16#10# + i, "data in order");
            end if;
        end loop;
        rd_en <= '0';
        wait for 0 ns;
        check(empty = '1' and unsigned(count) = 0, "empty after underflow");
        check(dout = x"14", "underflow kept dout");
        -- 3. Simultaneous read and write with one word stored
        din <= x"A0"; wr_en <= '1'; wait until falling_edge(clk);
        din <= x"A1"; rd_en <= '1'; wait until falling_edge(clk);
        wr_en <= '0'; rd_en <= '0';
        check(dout = x"A0" and unsigned(count) = 1, "read+write same cycle");
        if errors = 0 then
            report "PASS: overflow and underflow refused, order kept, count="
                   & integer'image(to_integer(unsigned(count)));
        end if;
        done <= true;
        wait;
    end process;
end architecture;

Output (both simulators, at 120 ns)

PASS: overflow and underflow refused, order kept, count=1

To convince yourself that the test has teeth, remove && !full from do_wr: the fifth write then overwrites the oldest word and the testbench reports FAIL: full with 4 words and FAIL: data in order.

On the board: putting the FIFO between the UART receiver and transmitter

Insert fifo_sync (8 bits wide, depth 16 or more) into the uart_echo design of Chapter 16: connect the receiver's valid and data to wr_en and din; start the transmitter when the FIFO is not empty and the transmitter is not busy, and pulse rd_en at the same time. Because dout arrives one cycle after rd_en, delay the transmitter's start by one cycle. Then paste a long line of text into the terminal: a short burst now comes back complete. For an endless stream, the transmitter must also be at least as fast as the sender (Problem 5 of Chapter 16).

7. Crossing clock domains: why binary pointers fail

Often the producer and consumer run on different clocks — a camera at 74.25 MHz feeding logic at 125 MHz, for example. Then the full flag (computed in the write clock domain) needs the read pointer, and the empty flag (read domain) needs the write pointer. Each pointer must cross into the other clock domain.

Chapter 15 showed that a single bit can be brought across with a two-flip-flop synchroniser. A multi-bit binary counter cannot. When the counter goes from 7 (0111) to 8 (1000), four bits change at once. They never arrive at exactly the same instant, and if the receiving clock samples during the change, each bit can independently be old or new — the received value can be anything from 0 to 15. A FIFO that believes the write pointer is 15 will read garbage.

The fix is the Gray code, a way of numbering in which consecutive values differ in exactly one bit, including the wrap-around from the last value back to 0:

decimal	0	1	2	3	4	5	6	7
binary	000	001	010	011	100	101	110	111
Gray	000	001	011	010	110	111	101	100

If only one bit is changing when the other clock samples, the synchroniser delivers either the old value or the new one — both are legal pointer values, merely possibly one count stale. Conversion is cheap:

\[ g = b \oplus (b \gg 1), \qquad b_{N-1} = g_{N-1}, \quad b_i = b_{i+1} \oplus g_i \]

gray_conv — binary to Gray and Gray to binary

Verilog

module gray_conv #(
    parameter N = 4
) (
    input  wire [N-1:0] bin_in,
    output wire [N-1:0] gray_out,     // binary -> Gray
    input  wire [N-1:0] gray_in,
    output reg  [N-1:0] bin_out       // Gray -> binary
);
    // Binary to Gray: each bit XOR the bit above it
    assign gray_out = bin_in ^ (bin_in >> 1);

    // Gray to binary: each bit is the XOR of all Gray bits at and above it
    integer i;
    always @(*) begin
        bin_out[N-1] = gray_in[N-1];
        for (i = N - 2; i >= 0; i = i - 1)
            bin_out[i] = bin_out[i+1] ^ gray_in[i];
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gray_conv is
    generic (
        N : positive := 4
    );
    port (
        bin_in   : in  std_logic_vector(N-1 downto 0);
        gray_out : out std_logic_vector(N-1 downto 0);   -- binary -> Gray
        gray_in  : in  std_logic_vector(N-1 downto 0);
        bin_out  : out std_logic_vector(N-1 downto 0)    -- Gray -> binary
    );
end entity;

architecture rtl of gray_conv is
begin
    -- Binary to Gray: each bit XOR the bit above it
    gray_out <= bin_in xor ('0' & bin_in(N-1 downto 1));

    -- Gray to binary: each bit is the XOR of all Gray bits at and above it
    process (gray_in)
        variable b : std_logic_vector(N-1 downto 0);
    begin
        b(N-1) := gray_in(N-1);
        for i in N - 2 downto 0 loop
            b(i) := b(i+1) xor gray_in(i);
        end loop;
        bin_out <= b;
    end process;
end architecture;

gray_conv_tb — round trip and the one-bit property over a full cycle

Verilog

`timescale 1ns/1ps
module gray_conv_tb;
    reg  [3:0] bin = 4'd0, prev_gray = 4'd0;
    wire [3:0] gray, back;
    integer i, k, ones, errors = 0;

    // Feed the Gray output straight back into the Gray-to-binary converter
    gray_conv #(.N(4)) dut (.bin_in(bin), .gray_out(gray), .gray_in(gray), .bin_out(back));

    initial begin
        for (i = 0; i <= 16; i = i + 1) begin
            bin = i[3:0]; #1;                    // i = 16 wraps to 0
            if (back !== bin) begin
                $display("FAIL: round trip %0d", i); errors = errors + 1;
            end
            if (i > 0) begin
                ones = 0;
                for (k = 0; k < 4; k = k + 1) ones = ones + (gray[k] ^ prev_gray[k]);
                if (ones != 1) begin
                    $display("FAIL: %0d bits changed at step %0d", ones, i); errors = errors + 1;
                end
            end
            prev_gray = gray;
        end
        if (errors == 0) $display("PASS: 16 round trips, exactly 1 bit changes per step (incl. wrap)");
        $finish;
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gray_conv_tb is
end entity;

architecture sim of gray_conv_tb is
    signal bin, gray, back : std_logic_vector(3 downto 0) := (others => '0');
begin
    -- Feed the Gray output straight back into the Gray-to-binary converter
    dut : entity work.gray_conv generic map (N => 4)
        port map (bin_in => bin, gray_out => gray, gray_in => gray, bin_out => back);

    process
        variable prev_gray : std_logic_vector(3 downto 0) := (others => '0');
        variable ones, errors : natural := 0;
    begin
        for i in 0 to 16 loop
            bin <= std_logic_vector(to_unsigned(i mod 16, 4)); wait for 1 ns;
            if back /= bin then
                report "FAIL: round trip " & integer'image(i); errors := errors + 1;
            end if;
            if i > 0 then
                ones := 0;
                for k in 0 to 3 loop
                    if gray(k) /= prev_gray(k) then ones := ones + 1; end if;
                end loop;
                if ones /= 1 then
                    report "FAIL: step " & integer'image(i); errors := errors + 1;
                end if;
            end if;
            prev_gray := gray;
        end loop;
        if errors = 0 then
            report "PASS: 16 round trips, exactly 1 bit changes per step (incl. wrap)";
        end if;
        wait;
    end process;
end architecture;

8. The dual-clock FIFO

The architecture below is the classic asynchronous FIFO. Each side keeps its own pointer in binary (for addressing and incrementing) and in Gray code (for export). Only the Gray copy crosses to the other domain, through two flip-flops. Full and empty are compared in Gray code directly: empty when the two Gray pointers are equal; full when they are one lap apart, which in Gray code means the top two bits are inverted and the rest equal.

Dual-clock FIFO. The RAM is written on wclk and read on rclk. Each pointer crosses to the other domain as a Gray code through a two-flip-flop synchroniser, so only one bit can be in transition.

fifo_async — dual-clock FIFO with Gray-coded pointers

Verilog

module fifo_async #(
    parameter DW = 8,
    parameter AW = 4                       // depth 2**AW, AW >= 2
) (
    // write clock domain
    input  wire          wclk,
    input  wire          wrst,
    input  wire          wr_en,
    input  wire [DW-1:0] din,
    output wire          full,
    // read clock domain
    input  wire          rclk,
    input  wire          rrst,
    input  wire          rd_en,
    output reg  [DW-1:0] dout = 0,
    output wire          empty
);
    reg [DW-1:0] mem [0:(1<<AW)-1];
    reg [AW:0] wbin = 0, wgray = 0;        // write pointer: binary and Gray
    reg [AW:0] rbin = 0, rgray = 0;        // read pointer: binary and Gray
    reg [AW:0] rgray_w1 = 0, rgray_w2 = 0; // read pointer, in write domain
    reg [AW:0] wgray_r1 = 0, wgray_r2 = 0; // write pointer, in read domain

    // ---------------- write domain ----------------
    wire        do_wr     = wr_en && !full;
    wire [AW:0] wbin_next = wbin + 1'b1;

    always @(posedge wclk) begin
        if (do_wr)
            mem[wbin[AW-1:0]] <= din;
        if (wrst) begin
            wbin  <= 0;
            wgray <= 0;
        end else if (do_wr) begin
            wbin  <= wbin_next;
            wgray <= wbin_next ^ (wbin_next >> 1);
        end
        rgray_w1 <= rgray;                 // 2-FF synchroniser: only one
        rgray_w2 <= rgray_w1;              // bit of rgray changes at a time
    end
    // Full: the pointers are one lap apart. In Gray code that means the
    // top two bits differ and all the others are equal.
    assign full = (wgray == {~rgray_w2[AW:AW-1], rgray_w2[AW-2:0]});

    // ---------------- read domain ----------------
    wire        do_rd     = rd_en && !empty;
    wire [AW:0] rbin_next = rbin + 1'b1;

    always @(posedge rclk) begin
        if (do_rd)
            dout <= mem[rbin[AW-1:0]];
        if (rrst) begin
            rbin  <= 0;
            rgray <= 0;
        end else if (do_rd) begin
            rbin  <= rbin_next;
            rgray <= rbin_next ^ (rbin_next >> 1);
        end
        wgray_r1 <= wgray;
        wgray_r2 <= wgray_r1;
    end
    assign empty = (rgray == wgray_r2);
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fifo_async is
    generic (
        DW : positive := 8;
        AW : positive := 4                    -- depth 2**AW, AW >= 2
    );
    port (
        -- write clock domain
        wclk  : in  std_logic;
        wrst  : in  std_logic;
        wr_en : in  std_logic;
        din   : in  std_logic_vector(DW-1 downto 0);
        full  : out std_logic;
        -- read clock domain
        rclk  : in  std_logic;
        rrst  : in  std_logic;
        rd_en : in  std_logic;
        dout  : out std_logic_vector(DW-1 downto 0);
        empty : out std_logic
    );
end entity;

architecture rtl of fifo_async is
    type mem_t is array (0 to 2**AW - 1) of std_logic_vector(DW-1 downto 0);
    subtype ptr_t is unsigned(AW downto 0);
    signal mem : mem_t;
    -- write domain
    signal wbin, wgray         : ptr_t := (others => '0');
    signal rgray_w1, rgray_w2  : ptr_t := (others => '0');
    signal wbin_next           : ptr_t;
    signal full_i, do_wr       : std_logic;
    -- read domain
    signal rbin, rgray         : ptr_t := (others => '0');
    signal wgray_r1, wgray_r2  : ptr_t := (others => '0');
    signal rbin_next           : ptr_t;
    signal empty_i, do_rd      : std_logic;
    signal dout_r : std_logic_vector(DW-1 downto 0) := (others => '0');
begin
    ---------------- write domain ----------------
    do_wr     <= wr_en and not full_i;
    wbin_next <= wbin + 1;

    process (wclk)
    begin
        if rising_edge(wclk) then
            if do_wr = '1' then
                mem(to_integer(wbin(AW-1 downto 0))) <= din;
            end if;
            if wrst = '1' then
                wbin  <= (others => '0');
                wgray <= (others => '0');
            elsif do_wr = '1' then
                wbin  <= wbin_next;
                wgray <= wbin_next xor shift_right(wbin_next, 1);
            end if;
            rgray_w1 <= rgray;                -- 2-FF synchroniser: only one
            rgray_w2 <= rgray_w1;             -- bit of rgray changes at a time
        end if;
    end process;
    -- Full: one lap apart = top two Gray bits differ, the others are equal.
    full_i <= '1' when wgray = ((not rgray_w2(AW downto AW-1)) & rgray_w2(AW-2 downto 0))
              else '0';
    full <= full_i;

    ---------------- read domain ----------------
    do_rd     <= rd_en and not empty_i;
    rbin_next <= rbin + 1;

    process (rclk)
    begin
        if rising_edge(rclk) then
            if do_rd = '1' then
                dout_r <= mem(to_integer(rbin(AW-1 downto 0)));
            end if;
            if rrst = '1' then
                rbin  <= (others => '0');
                rgray <= (others => '0');
            elsif do_rd = '1' then
                rbin  <= rbin_next;
                rgray <= rbin_next xor shift_right(rbin_next, 1);
            end if;
            wgray_r1 <= wgray;
            wgray_r2 <= wgray_r1;
        end if;
    end process;
    empty_i <= '1' when rgray = wgray_r2 else '0';
    empty   <= empty_i;
    dout    <= dout_r;
end architecture;

The testbench below writes on an 8 ns clock and reads on a 13 ns clock with no fixed phase relation. The reader starts late, so the 8-word FIFO fills up and full must hold the writer back; then 100 words must arrive in order. Both simulators print PASS: 100 words crossed clock domains in order at 1712 ns.

fifo_async_tb — 125 MHz writer, ~77 MHz reader

Verilog

`timescale 1ns/1ps
module fifo_async_tb;
    localparam N = 100;                       // words to transfer
    reg        wclk = 0, rclk = 0, wr_en = 0, rd_en = 0;
    reg  [7:0] din = 0;
    wire [7:0] dout;
    wire       full, empty;
    integer    sent = 0, got = 0, errors = 0, full_seen = 0, pending = 0;

    fifo_async #(.DW(8), .AW(3)) dut (
        .wclk(wclk), .wrst(1'b0), .wr_en(wr_en), .din(din), .full(full),
        .rclk(rclk), .rrst(1'b0), .rd_en(rd_en), .dout(dout), .empty(empty));

    always #4   wclk = ~wclk;                 // 125 MHz writer
    always #6.5 rclk = ~rclk;                 // ~77 MHz reader, unrelated phase

    // Writer: push 0, 1, 2, ... whenever the FIFO is not full
    always @(negedge wclk) begin
        if (full) full_seen = 1;
        wr_en = (sent < N) && !full;
        din   = sent;
        if (wr_en) sent = sent + 1;
    end

    // Reader: starts late (so the FIFO fills up), then pops every cycle
    always @(negedge rclk) begin
        if (pending) begin                    // data from the previous pop
            if (dout !== got[7:0]) begin
                $display("FAIL: got %0d expected %0d", dout, got); errors = errors + 1;
            end
            got = got + 1;
        end
        rd_en   = ($time > 300) && !empty;
        pending = rd_en;
    end

    initial begin
        wait (got == N);
        #100;
        if (errors == 0 && full_seen && empty)
            $display("PASS: %0d words crossed clock domains in order (full seen, empty at end)", got);
        else
            $display("FAIL: errors=%0d full_seen=%0d", errors, full_seen);
        $finish;
    end
endmodule

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fifo_async_tb is
end entity;

architecture sim of fifo_async_tb is
    constant N : natural := 100;              -- words to transfer
    signal wclk, rclk, wr_en, rd_en : std_logic := '0';
    signal din, dout  : std_logic_vector(7 downto 0) := (others => '0');
    signal full, empty : std_logic;
    signal got        : natural := 0;
    signal errors     : natural := 0;
    signal full_seen  : boolean := false;
    signal done       : boolean := false;
begin
    dut : entity work.fifo_async generic map (DW => 8, AW => 3)
        port map (wclk => wclk, wrst => '0', wr_en => wr_en, din => din, full => full,
                  rclk => rclk, rrst => '0', rd_en => rd_en, dout => dout, empty => empty);

    wclk <= not wclk after 4 ns   when not done;   -- 125 MHz writer
    rclk <= not rclk after 6.5 ns when not done;   -- ~77 MHz reader

    -- Writer: push 0, 1, 2, ... whenever the FIFO is not full
    writer : process (wclk)
        variable sent : natural := 0;
    begin
        if falling_edge(wclk) then
            if full = '1' then full_seen <= true; end if;
            if sent < N and full = '0' then
                wr_en <= '1';
                din   <= std_logic_vector(to_unsigned(sent mod 256, 8));
                sent  := sent + 1;
            else
                wr_en <= '0';
            end if;
        end if;
    end process;

    -- Reader: starts late (so the FIFO fills up), then pops every cycle
    reader : process (rclk)
        variable pending : boolean := false;
    begin
        if falling_edge(rclk) then
            if pending then
                if to_integer(unsigned(dout)) /= got mod 256 then
                    report "FAIL: got " & integer'image(to_integer(unsigned(dout)));
                    errors <= errors + 1;
                end if;
                got <= got + 1;
            end if;
            if now > 300 ns and empty = '0' then
                rd_en <= '1'; pending := true;
            else
                rd_en <= '0'; pending := false;
            end if;
        end if;
    end process;

    finish : process
    begin
        wait until got = N;
        wait for 100 ns;
        if errors = 0 and full_seen and empty = '1' then
            report "PASS: " & integer'image(got) &
                   " words crossed clock domains in order (full seen, empty at end)";
        else
            report "FAIL: errors=" & integer'image(errors);
        end if;
        done <= true;
        wait;
    end process;
end architecture;

A simulation pass is not a CDC proof

A logic simulator never shows metastability, so this testbench checks the bookkeeping, not the clock crossing itself. The correctness of the crossing rests on the Gray-code argument and on constraints: in Vivado, the paths from one clock to the other must be told not to be timed as ordinary paths (for instance with set_max_delay -datapath_only on the Gray pointer buses, or by declaring the clocks asynchronous). For production designs, Xilinx provides verified FIFO generators and the XPM macros; use the hand-written one to understand them.

9. Python: Gray codes and choosing a FIFO depth

The first part generates a 5-bit Gray code and verifies the one-bit-change property and the conversion back to binary. The second part answers the practical question “how deep must my FIFO be?” for a producer that writes in bursts of 64 words at full speed, then pauses, and a consumer that reads steadily at half speed. The average input rate (0.4 words/cycle) is below the read capacity (0.5), so the FIFO only has to absorb the bursts. An isolated burst leaves $64 \times (1 - 0.5) = 32$ words behind, but bursts that arrive before the FIFO has drained pile up: the simulated peak over 200 000 cycles is 80 words, so a depth of 128 is the right choice.

Python

script.py79 lines

import numpy as np
import matplotlib.pyplot as plt

# ---- 1. Gray code: generate, check the single-bit-change property ----
N = 5
codes = [b ^ (b >> 1) for b in range(2**N)]
changes = [bin(codes[i] ^ codes[(i + 1) % 2**N]).count('1') for i in range(2**N)]
def gray_to_bin(g):
    b = 0
    while g:
        b ^= g
        g >>= 1
    return b
round_trip = all(gray_to_bin(g) == b for b, g in enumerate(codes))
bin_changes = [bin(b ^ ((b + 1) % 2**N)).count('1') for b in range(2**N)]
print(f"{N}-bit Gray code: bits changed per step = {sorted(set(changes))} (incl. wrap 31->0)")
print(f"Gray->binary round trip correct: {round_trip}")
print(f"Binary counter: up to {max(bin_changes)} bits change at once (e.g. 01111 -> 10000)")

# ---- 2. FIFO sizing: bursty producer, steady consumer ----
# Producer: bursts of 64 words at one word per cycle, then a random pause
# of 32..160 cycles (mean 96), so the long-run average is 0.4 words/cycle.
# Consumer: steady, reads one word every 2 cycles (0.5 words/cycle) when not empty.
rng = np.random.default_rng(1)
T = 200_000
BURST = 64
writes = np.zeros(T, dtype=int)
t = 0
while t < T:
    writes[t:t + BURST] = 1
    t += BURST + int(rng.integers(32, 161))
occ, level = np.zeros(T, dtype=int), 0
for i in range(T):
    level += writes[i]
    if i % 2 == 0 and level > 0:           # consumer: one word every 2 cycles
        level -= 1
    occ[i] = level
need = occ.max()
depth = 1 << int(np.ceil(np.log2(need + 1)))
analytic = BURST * (1 - 0.5 / 1.0)         # burst length x (1 - r_read / r_write)
print(f"\nAverage write rate: {writes.mean():.3f} words/cycle, read capacity 0.5")
print(f"Peak occupancy: {need} words (one isolated burst needs {analytic:.0f})")
print(f"Choose depth {depth} (next power of two)")

# What a too-small FIFO would lose
for d in (16, 32, 64, depth):
    level, lost = 0, 0
    for i in range(T):
        if writes[i]:
            if level < d: level += 1
            else: lost += 1
        if i % 2 == 0 and level > 0: level -= 1
    print(f"  depth {d:>3}: {lost} words lost ({lost / writes.sum() * 100:.2f} %)")

plt.style.use('dark_background')
fig, (ax1, ax2) = plt.subplots(2, 1, figsize=(11, 7), gridspec_kw={'height_ratios': [1, 2]})
fig.patch.set_facecolor('#0a0a0a')
ax1.set_facecolor('#0f0f0f')
img = np.array([[(codes[i] >> (N - 1 - k)) & 1 for i in range(2**N)] for k in range(N)])
ax1.imshow(img, cmap='copper', aspect='auto', interpolation='nearest')
ax1.set_yticks(range(N)); ax1.set_yticklabels([f'bit {N-1-k}' for k in range(N)], fontsize=8)
ax1.set_xlabel('count value (binary 0 .. 31)')
ax1.set_title(f'{N}-bit Gray code: every step (and the wrap) flips exactly one bit', color='#fdba74', fontsize=11)

ax2.set_facecolor('#0f0f0f')
w = slice(0, 6000)
ax2.plot(np.arange(T)[w], occ[w], color='#fb923c', lw=1, label='FIFO occupancy')
ax2.fill_between(np.arange(T)[w], 0, writes[w] * 4, step='post', color='#38bdf8', alpha=0.35, label='producer burst active')
ax2.axhline(need, color='#fbbf24', ls='--', lw=1)
ax2.text(5900, need + 1.5, f'peak over {T:,} cycles = {need}', color='#fbbf24', ha='right', fontsize=9, bbox=dict(facecolor='#0f0f0f', edgecolor='none', pad=1))
ax2.axhline(16, color='#f87171', ls=':', lw=1)
ax2.text(5900, 17, "depth 16: overflows", color='#f87171', ha='right', fontsize=9, bbox=dict(facecolor='#0f0f0f', edgecolor='none', pad=1))
ax2.set_ylim(0, need * 1.35)
ax2.set_xlabel('clock cycle'); ax2.set_ylabel('words stored')
ax2.legend(loc='upper left', fontsize=8, framealpha=0.3)
for ax in (ax1, ax2):
    for sp in ax.spines.values(): sp.set_edgecolor('#374151')
plt.tight_layout()
plt.savefig('output.png', dpi=120, bbox_inches='tight', facecolor='#0a0a0a')

Click Run to execute the Python code

Code will be executed with Python 3 on the server

Key idea: a FIFO absorbs bursts, not rate differences

If the long-run input rate exceeds the output rate, no finite FIFO is deep enough — it only delays the overflow. Size a FIFO for the worst burst; fix the average rate with the design itself.

Practice Problems

Progress: 0/5 (0%)

⭐ Easy

How many 36 Kb block RAMs does Vivado need for (a) a 1024 × 16 memory, (b) a 4096 × 32 memory, (c) a 512 × 64 simple dual-port memory?

⭐ Easy

Write the 4-bit Gray code for the decimal values 5, 6 and 7, and show that consecutive codes differ in one bit. Then convert the Gray code 1101 back to binary.

⭐⭐ Medium

A FIFO of depth 8 uses 3-bit pointers only (no extra bit). After reset both pointers are 0. (a) Why can it not tell full from empty? (b) Name another fix besides the extra bit, and its cost.

⭐⭐ Medium

A camera delivers lines of 640 pixels at 1 pixel per cycle with 160 idle cycles between lines. A processing block consumes 1 pixel every 1.2 cycles on average, without pauses. What FIFO depth is needed between them, and is the system sustainable?

⭐⭐⭐ Hard

In the dual-clock FIFO, the read side sees the write pointer two read-clock cycles late. Explain why empty can stay high for a few cycles after a word was written, but can never go low while the FIFO is really empty. Is the same "safe direction" true for full?

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